Connect A, GATE and C pins of LM74721-Q1 close to
the MOSFET SOURCE, GATE and DRAIN pins for the ideal diode stage, c.
Use thick and short traces for source and drain
of the MOSFET to minimize resistive losses because
the high current path of for this solution is
through the MOSFET.
Have the PowerPAD™ integrated circuit package (exposed pad) of
the MOSFET soldered directly to the top plane for best thermal performance.
Other planes, such as the bottom side of the circuit board, can be used to
increase heat sinking. Thermal considerations: during the VDS clamp operation,
the MOSFET acts as an active clamp with pulse power dissipation.
Connect the GATE pin of the LM74721-Q1 to the
MOSFET GATE with short trace.
Minimize the loops formed by capacitor across CAP
pin and DRAIN of the FET and C3 to GND by placing
these capacitors as close as possible. Keep the
GND side of the C3 capacitor close to GND pin of
LM74721-Q1. Boost converter switching currents
flow into LX, CAP, GND pins and C3 (across DRAIN
of the FET to GND).
Place transient suppression components like
output Schottky close to C pin of LM74721-Q1.