ZHCSLG2B September   2021  – August 2022 LM74722-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Dual Gate Control (GATE, PD)
        1. 8.3.1.1 Reverse Battery Protection (A, C, GATE)
        2. 8.3.1.2 Load Disconnect Switch Control (PD)
        3. 8.3.1.3 Overvoltage Protection and Battery Voltage Sensing (VSNS, SW, OV)
      2. 8.3.2 Boost Regulator
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical 12-V Reverse Battery Protection Application
      1. 9.2.1 Design Requirements for 12-V Battery Protection
        1. 9.2.1.1 Automotive Reverse Battery Protection
          1. 9.2.1.1.1 Input Transient Protection: ISO 7637-2 Pulse 1
          2. 9.2.1.1.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
          3. 9.2.1.1.3 Input Micro-Short Protection: LV124 E-10
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Design Considerations
        2. 9.2.2.2 Boost Converter Components (C2, C3, L1)
        3. 9.2.2.3 Input and Output Capacitance
        4. 9.2.2.4 Hold-Up Capacitance
        5. 9.2.2.5 Overvoltage Protection and Battery Monitor
        6. 9.2.2.6 MOSFET Selection: Blocking MOSFET Q1
        7. 9.2.2.7 MOSFET Selection: Load Disconnect MOSFET Q2
        8. 9.2.2.8 TVS Selection
      3. 9.2.3 Application Curves
    3. 9.3 What to Do and What Not to Do
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 TVS Selection for 12-V Battery Systems
    3. 10.3 TVS Selection for 24-V Battery Systems
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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6.6 Switching Characteristics

TJ = –40°C to +125°C; typical values at TJ = 25°C, V(A) = V(C) = 12 V, C(CAP) = 1 µF, V(EN) = 2 V, over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tA_POR(DLY) A (low to high) to GATE turn-on delay V(A) ↑ V(A POR)  to V(GATE – A) > 5 V, C((GATE – A) = 10  nF 200 µs
tGATE_ON(DLY) Forward voltage detection to GATE turn-on delay V(A) – V(C) = –100 mV to 700 mV, V(GATE – A) > 5 V, C((GATE – A) = 10  nF 0.72 1.25 µs
V(A) – V(C) = –100 mV to 700 mV, V(GATE – A) > 5 V, C((GATE – A) = 30  nF 1.02 1.9 µs
tGATE_OFF(DLY) Reverse voltage detection to GATE turn-off delay V(A) – V(C) = +30 mV to –100 mV, V(GATE – A) < 1 V, C((GATE – A) = 10  nF 0.46 0.65 µs
tEN_OFF(DLY)PD EN to PD Delay EN ↓ to PD ↓ 6.5 12 µs
tOV_OFF(DLY)PD OV to PD Deglitch OV ↑ to PD ↓ 0.9 1.5 µs
tPD_Pk Peak Pull Down duration I(PD_SINK,Pk)   ↑ to     I(PD_SINK,DC) ↓ 11 38 65 µs
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