ZHCSLA3A May 2020 – December 2020 LM7481-Q1
PRODUCTION DATA
Figure 8-6 shows the implementation of Dual OR-ing with Inrush Current Limiting, Over Voltage Protection and power path ON/OFF control. The input side SMBJ36CA TVS across the ideal diodes is required for ISO7637 Pulse 1 transient suppression to limit the input voltage within the device max voltage rating of –65 V.
R1 and R2 are the programming resistors for over voltage protection (OVP) threshold. When the voltage at OVP pin exceeds OVP cut-off reference threshold then the HGATE driver turns OFF the FET Q3, disconnecting the power path and protecting the downstream load. HGATE goes high once the OVP pin voltage goes below the OVP falling hysteresis threshold. Use 0.1-μF to 1-μF capacitor across VS to CAP pins of the LM74810-Q1. This is the charge pump capacitor and acts as the supply for both the DGATE and HGATE driver stages. The DGATE driver of the LM74810-Q1 is equipped with 60-mA peak source current and 1.5-A peak sink current capability resulting in fast and efficient transient responses during the ISO16750 or LV124 short interruptions as well as AC superimpose testing.
Pull EN low during the sleep/standby mode. With EN low, both the DGATE and HGATE drivers are pulled low turning OFF both the power FETs. VOUT1 gets disconnected from the VBATT rail reducing the system IQ. VOUT2 is gets power through the body diode of the MOSFET Q2 and this supply can be utilized for always ON loads. The LM74810-Q1 draws a 2.87-μA current during this mode.