ZHCSO86B december   2022  – july 2023 LM74900-Q1 , LM74910-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 开关特性
    7. 7.7 Typical Characteristics
  9. 8 Parameter Measurement Information
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Charge Pump
      2. 9.3.2 Dual Gate Control (DGATE, HGATE)
        1. 9.3.2.1 Reverse Battery Protection (A, C, DGATE)
        2. 9.3.2.2 Load Disconnect Switch Control (HGATE, OUT)
      3. 9.3.3 Overcurrent Protection (CS+, CS-, ILIM, IMON, TMR)
        1. 9.3.3.1 Pulse Overload Protection, Circuit Breaker
        2. 9.3.3.2 Overcurrent Protection With Latch-Off
        3. 9.3.3.3 Short Circuit Protection (ISCP)
        4. 9.3.3.4 Analog Current Monitor Output (IMON)
      4. 9.3.4 Undervoltage Protection, Overvoltage Protection, and Battery Voltage Sensing (UVLO, OV, SW)
      5. 9.3.5 Low IQ SLEEP Mode (SLEEP)
      6. 9.3.6 Ultra Low IQ Shutdown (EN)
  11. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical 12-V Reverse Battery Protection Application
      1. 10.2.1 Design Requirements for 12-V Battery Protection
      2. 10.2.2 Automotive Reverse Battery Protection
        1. 10.2.2.1 Input Transient Protection: ISO 7637-2 Pulse 1
        2. 10.2.2.2 AC Super Imposed Input Rectification: ISO 16750-2 and LV124 E-06
        3. 10.2.2.3 Input Micro-Short Protection: LV124 E-10
      3. 10.2.3 Detailed Design Procedure
        1. 10.2.3.1 Design Considerations
        2. 10.2.3.2 Charge Pump Capacitance VCAP
        3. 10.2.3.3 Input and Output Capacitance
        4. 10.2.3.4 Hold-Up Capacitance
        5. 10.2.3.5 Selection of Current Sense Resistor, RSNS
        6. 10.2.3.6 Selection of Scaling Resistor (RSET) and Short-Circuit Protection Setting Resistor (RSCP)
        7. 10.2.3.7 Overcurrent Limit (ILIM), Circuit Breaker Timer (TMR), and Current Monitoring Output (IMON) Selection
        8. 10.2.3.8 Overvoltage Protection and Battery Monitor
      4. 10.2.4 MOSFET Selection: Blocking MOSFET Q1
      5. 10.2.5 MOSFET Selection: Hot-Swap MOSFET Q2
      6. 10.2.6 TVS Selection
      7. 10.2.7 Application Curves
    3. 10.3 Addressing Automotive Input Reverse Battery Protection Topologies With LM749x0-Q1
    4. 10.4 Power Supply Recommendations
      1. 10.4.1 Transient Protection
      2. 10.4.2 TVS Selection for 12-V Battery Systems
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
  12. 11Device and Documentation Support
    1. 11.1 接收文档更新通知
    2. 11.2 支持资源
    3. 11.3 Trademarks
    4. 11.4 静电放电警告
    5. 11.5 术语表
  13. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6 开关特性

TJ = –40°C 至 +125°C；TJ = 25°C、V(A) = V(OUT) = V(VS) = 12V、C(CAP) = 0.1µF、V(EN)、V(SLEEP) = 2V 时的典型值，在自然通风条件下的工作温度范围内（除非另有说明）
参数 测试条件 最小值 典型值 最大值 单位
tDGATE_OFF(dly) 反向电压检测期间的 DGATE 关断延迟 V(A) – V(C) = +30mV 至 –100mV 至 V(DGATE–A) < 1V，C(DGATE–A) = 10nF 0.5 0.95 µs
tDGATE_ON(dly) 正向电压检测期间的 DGATE 导通延迟 V(A)–V(C) = –20mV 至 +700mV 至 V(DGATE-A) > 5V，C(DGATE-A) = 10nF，仅限 LM74900-Q1 2 3.8 µs
tDGATE_ON(dly) 正向电压检测期间的 DGATE 导通延迟 V(A)–V(C) = –20mV 至 +700mV 至 V(DGATE-A) > 5V，C(DGATE-A) = 10nF，仅限 LM74910-Q1 0.75 1.6 µs
tEN(dly)_DGATE EN 期间的 DGATE 导通延迟 EN ↑ 至 V(DGATE-A) > 5V，C(DGATE-A) = 10nF 180 270 µs
tUVLO_OFF(deg)_HGATE UVLO 期间的 HGATE 关断抗尖峰脉冲 UVLO ↓ 至 HGATE ↓ 5 7 µs
tUVLO_ON(deg)_HGATE UVLO 期间的 HGATE 关断抗尖峰脉冲 UVLO ↑ 至 HGATE ↑  8.5 µs
tOVP_OFF(deg)_HGATE OV 期间的 HGATE 关断抗尖峰脉冲 OV ↑ 至 HGATE ↓ 4 7 µs
tOVP_ON(deg)_HGATE OV 期间的 HGATE 关断抗尖峰脉冲 OV ↓ 至 HGATE ↑ 9 µs
tSCP_DLY 短路保护关闭延迟 (VISCP - VCS-) = 0mv 至 100mV HGATE↓，CGS = 4.7nF 3 5.5 µs
tOCP_TMR_DLY 过流保护关闭延迟 (VCS+ - VCS-)↑ HGATE↓，CTMR = 50pF
 		 35 µs
过流保护关闭延迟 (VCS+ - VCS-)↑ HGATE↓，CTMR = 10nF 190 µs
tAUTO_RETRY_DLY 过流/短路保护自动重试延迟 (VCS+ - VCS-) ↓ HGATE ↑，CTMR = 50pF
 		 1.5 ms
过流/短路保护自动重试延迟 (VCS+ - VCS-) ↓ HGATE ↑，CTMR = 10nF
 		 230 ms
tFLT_ASSERT 故障置位延迟 (VCS+ - VCS-)↑ FLT↓，CTMR = 50pF
 		 35 µs
故障置位延迟 OV ↑ 至 FLT ↓ 3 µs
tFLT_DE-ASSERT 故障取消置位延迟 4 µs
tSLEEP_OCP_LATCH 睡眠 OCP 锁存延迟 3.5 7.5 µs
tSLEEP_MODE 睡眠模式进入延迟 SLEEP=低电平，EN=高电平 95 µs
tOVCLAMP OV 钳位响应延迟  3.5 µs
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