Placements shown in Figure 8-7 and in the cross section of Figure 8-8 show the suggested placement of the device with respect to sensitive passive components, such as VIN, bootstrap capacitors (HS and HB) and VSS capacitors. Use appropriate spacing in the layout to reduce creepage and maintain clearance requirements in accordance with the application pollution level. Inner layers if present can be more closely spaced due to negligible pollution.

The layout must be designed to minimize the capacitance at the SW node. Use as small an area of copper as possible to connect the device SW pin to the inductor, or transformer, or other output load. Furthermore, ensure that the ground plane or any other copper plane has a cutout so that there is no overlap with the SW node, as this would effectively form a capacitor on the printed circuit board. Additional capacitance on this node reduces the advantages of the advanced packaging approach of the LMG2100R044 and may result in reduced performance.

Figure 8-7 External Component Placement (Multi-layer PCB)

Figure 8-8 Four-Layer Board Cross Section With Return Path Directly Underneath for Power Loop

Figure 8-9 External Component Placement (Double Layer PCB)

Figure 8-10 Two-Layer Board Cross Section With Return Path

Two-layer boards are not recommended for use with LMG2100R044 device due to the larger power loop inductance. However, if design considerations allow only two board layers, place the input decoupling capacitors immediately behind the device on the back-side of the board to minimize loop inductance. Figure 8-9 and Figure 8-10 show a layout example for two-layer boards.