ZHCSNW8A October   2022  – December 2022 LMG2610

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 GaN Power FET Switching Parameters
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  GaN Power FET Switching Capability
      2. 8.3.2  Turn-On Slew-Rate Control
      3. 8.3.3  Current-Sense Emulation
      4. 8.3.4  Bootstrap Diode Function
      5. 8.3.5  Input Control Pins (EN, INL, INH)
      6. 8.3.6  INL - INH Interlock
      7. 8.3.7  AUX Supply Pin
        1. 8.3.7.1 AUX Power-On Reset
        2. 8.3.7.2 AUX Under-Voltage Lockout (UVLO)
      8. 8.3.8  BST Supply Pin
        1. 8.3.8.1 BST Power-On Reset
        2. 8.3.8.2 BST Under-Voltage Lockout (UVLO)
      9. 8.3.9  Over-Current Protection
      10. 8.3.10 Over-Temperature Protection
      11. 8.3.11 Fault Reporting
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Turn-On Slew-Rate Design
        2. 9.2.2.2 Current-Sense Design
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Solder-Joint Stress Relief
        2. 9.4.1.2 Signal-Ground Connection
        3. 9.4.1.3 CS Pin Signal
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
  • RRG|40
散热焊盘机械数据 (封装 | 引脚)
订购信息

Current-Sense Emulation

The current-sense emulation function creates a scaled replica of the low-side GaN power FET positive drain current at the output of the CS pin. The current-sense emulation gain, GCSE, is 1 mA output from the CS pin, ICS for every 1 A passing into the drain of the low-side GaN power FET, ID.

Equation 1. GCSE = ICS / ID = 1 mA / 1 A = 0.001

The CS pin is terminated with a resistor to AGND, RCS, to create the current-sense voltage input signal to the external power supply controller.

RCS is determined by solving for the traditional current-sense design resistance, RCS(trad), and multiplying by the inverse of GCSE. The traditional current-sense design creates the current-sense voltage, VCS(trad), by passing the low-side GaN power FET drain current, ID, through RCS(trad). The LMG2610 creates the current-sense voltage, VCS, by passing the CS pin output current, ICS, through RCS. The current-sense voltage must be the same for both designs.

Equation 2. VCS = ICS * RCS = VCS(trad) = ID * RCS(trad)
Equation 3. RCS = ID / ICS * RCS(trad) = 1 / GCSE * RCS(trad)
Equation 4. RCS = 1000 * RCS(trad)

The CS pin is clamped internally to a typical 2.5 V. The clamp protects vulnerable power-supply controller current-sense input pins from over voltage if, for example, the current sense resistor on the CS pin were to become disconnected.

Figure 8-2 shows the current-sense emulation operation. In both cycles, the CS pin current emulates the low-side GaN power-FET drain current while the low-side FET is enabled. The first cycle shows normal operation where the controller turns off the low-side GaN power FET when the controller current-sense input threshold is tripped. The second cycle shows a fault situation where the LMG2610 Over-Current Protection turns off the low-side GaN power FET before the controller current-sense input threshold is tripped. In this second cycle, the LMG2610 avoids a hung controller INL pulse by generating a fast-ramping artificial current-sense emulation signal to trip the controller current-sense input threshold. The artificial signal persists until the INL pin goes to logic-low which indicates the controller is back in control of switch operation.



Figure 8-2 Current-Sense Emulation Operation