The gate drive loop impedance must be minimized to obtain good performance. Although the gate driver is integrated on package, the bypass capacitance for the driver is placed externally. As the GaN device is turned off to a negative voltage, the impedance of the path to the external VNEG capacitor is included in the gate drive loop. The VNEG capacitor must be placed close to VNEG and SOURCE pins. In the Section 8.5.2, the bypass capacitors, C3 and C13, are located in the top layer and are connected to VNEG pins with vias and SOURCE pins through the local signal ground plane.

The VDD pin bypass capacitors, C1 and C11, must also be placed close to the VDD pin with low impedance connections.