10.2.2 Detailed Design Procedure

In a typical application, TI recommends the following steps:

1. The LMK05028 GUI in the TICS Pro programming software has a step-by-step design flow to enter the design parameters, calculate the frequency plan for each PLL domain, and generate the register settings for the desired configuration. The register settings can be exported (in hex format) to enable host programming or factory pre-programming.
   • If using a generic (non-custom) device, a host device can program the register settings through the serial interface after power-up and issue a soft-reset (by RESET_SW bit) to start the device. The host can also store the settings to the EEPROM to allow self-startup with these register settings on subsequent power-on reset cycles.
   • Alternatively, a LMK05028 setup file for TICS Pro (.tcs) can be sent to TI to request custom factory pre-programmed devices.
2. Tie the HW_SW_CTRL pin to ground to select EEPROM+I²C mode, or bias the pin to V_IM through the weak internal resistors or external resistors to select EEPROM+SPI mode. Determine the logic I/O pin assignments for control and status functions. See Device Start-Up Modes.
   • Connect I²C/SPI and logic I/O pins (1.8-V compatible levels) to the host device pins with the proper I/O direction and voltage levels.
3. Select a XO frequency by following Oscillator Input (XO_P/N).
   • Choose a XO with target phase jitter performance < 300 fs RMS (12 kHz to 20 MHz).
   • For a 3.3-V LVCMOS driver, follow the OSC clock interface example in Figure 67. Power the OSC from a low-noise LDO regulator or optimize its supply filtering to avoid supply-induced jitter on the XO clock.
   • TICS Pro: Configure the XO input buffer mode to match the XO driver interface requirements. See Table 4.
4. If a TCXO/OCXO is needed, select the frequency by following TCXO/OCXO Input (TCXO_IN).
   • Choose a TCXO/OCXO that meets the frequency stability and accuracy requirements required for the output clocks during free-run or holdover.
   • For a 3.3-V LVCMOS driver, follow the OSC clock interface example in Figure 67.
   • A (clipped) sinewave TCXO/OCXO with less than 1.3-Vpp swing can be simply AC-coupled to the input pin.
   • TICS Pro: The TCXO/OCXO input buffer is enabled when either PLL channel uses the TCXO-DPLL.
5. For each PLL domain, wire the clock I/O in the schematic and use TICS Pro to configure the device settings as follows:
   • Reference inputs: Follow the LVCMOS or differential clock input interface examples in Figure 67 or Clock Input Interfacing and Termination.
     • TICS Pro: Configure the reference input buffer modes to match the reference clock driver interface requirements. See Table 5.
     • LVCMOS clock input should be used for input frequencies below 5 MHz when amplitude monitoring is enabled.
   • TICS Pro: Configure the DPLL input selection modes and input priorities. See Reference Input Mux Selection.
   • TICS Pro: Output clock assignment guidelines to minimize crosstalk and spurs.
     • OUT[4:7] bank requires at least one clock from the PLL1 domain. OUT[4:7] bank is preferred for PLL1 clocks.
     • OUT[0:3] bank requires at least one clock from the PLL2 domain (if PLL2 is enabled). OUT[0:3] bank is preferred for PLL2 clocks.
     • Group identical output frequencies (or harmonic frequencies) on adjacent channels, and use the output pairs with a single divider (OUT2/3 or OUT4/5) when possible to minimize power.
     • Separate clock outputs when the difference of the two frequencies, |f_OUTx – f_OUTy|, falls within the jitter integration bandwidth (12 kHz to 20 MHz, for example). Any outputs that are potential aggressors should be separated by at least four static pins (power pin, logic pin, or disabled output pins) to minimize potential coupling. If possible, separate these clocks by the placing them on opposite output banks, which are on opposite sides of the chip for best isolation.
     • Avoid or isolate any LVCMOS output (strong aggressor) from other jitter-sensitive differential output clocks. If a LVCMOS output is required, use dual complementary LVCMOS mode (+/- or -/+) with the unused LVCMOS output left floating with no trace. Furthermore, the output slew rate could also be slowed to Normal mode (CHx_SLEW_RATE bit) to reduce the coupling strength of an LVCMOS output.
     • If not all outputs pairs are used in the application, consider connecting OUT0 and/or OUT1 to a pair of RF coaxial test structures for testing purposes (such as SMA, SMP ports). OUT0 and OUT1 are capable of selecting a buffered copy of the XO clock or the TCXO/Ref Bypass clock as well as any PLL post-divider clock.
   • TICS Pro: Configure output divider and drivers.
     • Configure the output driver modes to match the receiver clock input interface requirements. See Table 9.
     • Configure any output SYNC groups that need their output phases synchronized. See Output Synchronization (SYNC).
     • Configure the output auto-mute modes, output mute levels, and APLL and DPLL mute options. See Output Auto-Mute During LOL or LOS.
   • Clock output Interfacing: Follow the single-ended or differential clock output interface examples in Figure 67 or Clock Output Interfacing and Termination.
     • Differential outputs should be AC-coupled and terminated and biased at the receiver inputs.
     • HCSL outputs should have 50-Ω termination to GND (at source or load side) unless the internal source termination is enabled by programming.
     • LVCMOS outputs have internal source termination to drive 50-Ω traces directly. LVCMOS V_OH level is determined by VDDO voltage (1.8 V and 2.5 V).
   • TICS Pro: Configure the PLL loop mode. See PLL Configurations for Common Applications.
     • 3-Loop mode: Supports standards-compliant synchronization using a low-cost holdover TCXO/OCXO, very low loop bandwidths (≤10 Hz), or both. 3-loop mode also supports 1-PPS input synchronization.
     • 2-Loop REF-DPLL mode: Supports higher loop bandwidth (>10 Hz) and relaxed holdover stability without a TCXO/OCXO.
     • 2-Loop TCXO-DPLL mode: Locks to a TCXO/OCXO input and is typically used with DCO mode enabled for external clock steering (such as IEEE 1588 PTP).
   • TICS Pro: Configure the REF-DPLL loop bandwidth.
     • Below the loop bandwidth, the reference noise is added to the REF-TDC noise floor (and the XO noise in 2-loop mode). Above the loop bandwidth, the reference noise will be attenuated with roll-off up to 60 dB/decade. The optimal bandwidth depends on the relative phase noise between the reference input and the XO (2-loop mode) or the TCXO (3-loop mode).
     • 3-Loop mode: The bandwidth is typically 10 mHz to 10 Hz to attenuate wander, or determined by the applicable standard specification.
     • 2-Loop mode: The bandwidth is typically 10 Hz or higher. Target a bandwidth below 200 Hz if the PLL VCO frequency is an integer multiple of the reference input frequency.
   • TICS Pro: Configure the TCXO-DPLL loop bandwidth.
     • The optimal bandwidth depends on the relative phase noise between the TCXO/OCXO and the XO. Below the loop bandwidth, the TCXO/OCXO noise is added to the TCXO-TDC noise floor. Above the loop bandwidth, the OCXO/TCXO noise will be attenuated.
     • 3-Loop mode: The bandwidth should be at least 50x higher than the REF-DPLL bandwidth for loop stability.
     • 2-Loop TCXO-DPLL mode: Target a bandwidth below 300 Hz if the PLL VCO frequency is an integer multiple of the TCXO/OCXO frequency.
   • TICS Pro: Configure the Market Segment parameter to optimize the DPLL for the desired use case.
     • SyncE/SONET: REF-TDC rate is targeted for approximately 400 kHz. Hitless switching is enabled. This supports SyncE/SONET and other use cases using a narrow loop bandwidth (≤10 Hz) in 3-loop mode with a TCXO/OCXO to set the frequency stability and wander performance.
     • Wireless/BTS: REF-TDC rate is maximized for lowest in-band TDC noise contribution. Hitless switching is enabled. Supports wireless and other use cases where close-in phase noise is critical. This is used to achieve –112 dBc/Hz at 100-Hz offset for a 122.88-MHz output.
     • OTN/JitterAtten: REF-TDC rate is targeted for approximately 1 MHz. Hitless switching is disabled. Supports OTN/OTU and traditional jitter cleaning use cases with wider bandwidths (>10 Hz) in 2-loop mode and relaxed holdover frequency accuracy (no TCXO/OCXO).
   • TICS Pro: If clock steering is needed (such as for IEEE 1588 PTP), configure DCO mode for the REF or TCXO loop and enter the frequency step size (in ppb). The FDEV step register will be computed according to DCO Frequency Step Size. To allow DCO frequency updates using the external control pins, enable the FINC/FDEC functionality on the needed GPIO pins by setting the appropriate register bits (GPIO[3:6]_FDEV_EN).
   • TICS Pro: If deterministic input-to-output clock phase is needed, configure Zero-Delay mode and select the primary output channel that must be phase-aligned with the input. For DPLL1, any output from the OUT[4:7] bank can be selected for zero-delay feedback. For DPLL2, any output from the OUT[0:3] bank can be selected for zero-delay feedback. See Zero-Delay Mode (ZDM) Configuration.
6. TICS Pro: Configure the reference input monitoring options for each reference input. Disable the monitor when not required or when the input operates beyond the monitor's supported frequency range. See Reference Input Monitoring.
   • Amplitude monitor: Set the LVCMOS detected slew rate edge or the differential input amplitude threshold to monitor input signal quality. Disable the monitor for a differential input below 5 MHz or else use LVCMOS input clock.
   • Frequency monitor: Set the valid and invalid thresholds (in ppm).
   • Missing pulse monitor: Set the late window threshold (T_LATE) to allow for the longest expected input clock period, including worst-case cycle-to-cycle jitter. For a gapped clock input, set T_LATE based on the number of allowable missing clock pulses.
   • Runt pulse monitor: Set the early window threshold (T_EARLY) to allow for the shortest expected input clock period, including worst-case cycle-to-cycle jitter.
   • 1-PPS Phase validation monitor: Set the phase validation jitter threshold, including worst-case input cycle-to-cycle jitter.
   • Validation timer: Set the amount of time the reference input must be qualified by all enabled input monitors before the input is valid for selection.
7. TICS Pro: Configure the DPLL lock detect and tuning word history monitoring options for each channel. See PLL Lock Detectors and Tuning Word History.
   • DPLL tuning word history: Set the history count/averaging time (T_AVG), history delay/ignore time (T_IGN), and intermediate averaging option.
   • DPLL frequency lock and phase lock detectors: Set the lock and unlock thresholds for each detector.
8. TICS Pro: Configure each status output pin and interrupt flag as needed. See Status Outputs and Interrupt.
   • Select the desired status signal selection, status polarity, and driver mode (3.3-V LVCMOS or open-drain). Open-drain requires an external pullup resistor.
   • If the Interrupt is enabled and selected as a status output, configure the mask bit for any interrupt source to be ignored, interrupt flag polarity, and the combinational gate logic (AND/OR) as desired.