The XO input has a coarse frequency monitor to help qualify the input before it is used to lock the APLLs.

The XO frequency detector clears the LOS_FDET_XO flag when the input frequency is detected within the range of 9 MHz to 160 MHz to cover the supported XO input frequency range. The XO frequency monitor uses a RC-based detector and therefore cannot precisely determine whether XO input clock has sufficient frequency stability. A stable XO input will ensure successful VCO calibration of APLL2 or APLL1 during the PLL start-up. When the external XO clock has a slow or delayed start-up behavior TI recommends to force a calibration on APLL2 and APLL1 once the XO input is stable. See Section 9.1.7 for more information.

The XO frequency detector can be bypassed by setting the XO_FDET_BYP bit (shown as EN in Figure 8-15) so that the XO input is always considered valid by the PLL control state machine. The user can observe the LOS_FDET_XO status flag through the status pins and status bit. Setting XO_FDET_BYP bit will bypass the detect, but will not reflect any change to LOS_FDET_XO status flag.