ZHCSFR2B December   2016  – March 2018 LMR23630-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
      2.      效率与负载间的关系，VIN = 12V，PFM 选项
  4. 4 修订历史记录
  5. 5 Product Portfolio
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency Peak-Current-Mode Control
      2. 8.3.2  Adjustable Frequency
      3. 8.3.3  Adjustable Output Voltage
      4. 8.3.4  Enable/Synchronization
      5. 8.3.5  VCC, UVLO
      6. 8.3.6  Minimum ON-time, Minimum OFF-time and Frequency Foldback at Dropout Conditions
      7. 8.3.7  Power Good (PGOOD)
      8. 8.3.8  Internal Compensation and CFF
      9. 8.3.9  Bootstrap Voltage (BOOT)
      10. 8.3.10 Overcurrent and Short-Circuit Protection
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Active Mode
      3. 8.4.3 CCM Mode
      4. 8.4.4 Light Load Operation (PFM Option)
      5. 8.4.5 Light Load Operation (FPWM Option)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Output Voltage Setpoint
        3. 9.2.2.3  Switching Frequency
        4. 9.2.2.4  Inductor Selection
        5. 9.2.2.5  Output Capacitor Selection
        6. 9.2.2.6  Feed-Forward Capacitor
        7. 9.2.2.7  Input Capacitor Selection
        8. 9.2.2.8  Bootstrap Capacitor Selection
        9. 9.2.2.9  VCC Capacitor Selection
        10. 9.2.2.10 UVLO Setpoint
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Compact Layout for EMI Reduction
      2. 11.1.2 Ground Plane and Thermal Considerations
      3. 11.1.3 Feedback Resistors
    2. 11.2 Layout Examples
  12. 12器件和文档支持
    1. 12.1 使用 WEBENCH® 工具创建定制设计
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

DDA Package
8-Pin SOIC With PowerPAD
Top View
LMR23630-Q1 lmr23630-q1-pinout-soic-8-top-view-snvsar6.gif
DRR Package
12-Pin WSON With RT and Thermal Pad
Top View
LMR23630-Q1 lmr23630-q1-pinout-wson-12-top-view-snvsar6.gif
DRR Package
12-Pin WSON With PGOOD and Thermal Pad
Top View
LMR23630-Q1 lmr23630-q1-pinout-wson-12-pgood-top-view-snvsar6.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NAME SOIC WSON With PGOOD WSON With RT
SW 1 1, 2 1, 2 P Switching output of the regulator. Internally connected to both power MOSFETs. Connect to power inductor.
BOOT 2 3 3 P Boot-strap capacitor connection for high-side driver. Connect a high-quality, 100-nF capacitor from BOOT to SW.
VCC 3 4 4 P Internal bias supply output for bypassing. Connect a 2.2-μF, 16-V or higher capacitance bypass capacitor from this pin to AGND. Do not connect external loading to this pin. Never short this pin to ground during operation.
FB 4 5 5 A Feedback input to regulator, connect the midpoint of feedback resistor divider to this pin.
RT N/A N/A 6 A Connect a resistor RT from this pin to AGND to program switching frequency. Leave floating for 400-kHz default switching frequency.
PGOOD N/A 6 N/A A Open drain output for power-good flag. Use a 10-kΩ to 100-kΩ pullup resistor to logic rail or other DC voltage no higher than 12 V.
EN/SYNC 5 8 8 A Enable input to regulator. High = On, Low = Off. Can be connected to VIN. Do not float. Adjust the input undervoltage lockout with two resistors. The internal oscillator can be synchronized to an external clock by coupling a positive pulse into this pin through a small coupling capacitor. See Enable/Synchronization for details.
AGND 6 7 7 G Analog ground pin. Ground reference for internal references and logic. Connect to system ground.
VIN 7 9, 10 9, 10 P Input supply voltage.
PGND 8 12 12 G Power ground pin, connected internally to the low side power FET. Connect to system ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible.
PAD 9 13 13 G Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation path of the die. Must be used for heat sinking to ground plane on PCB.
NC N/A 11 11 N/A Not for use. Leave this pin floating.
(1) A = Analog, P = Power, G = Ground.
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