米6体育平台手机版

ZHCSGL5C March 2017 – April 2019 LMX2594

PRODUCTION DATA.

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RHA|40
- MPQF135D

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- QFND114P

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6.5 Electrical Characteristics

3.15 V ≤ V_CC ≤ 3.45 V, –40°C ≤ T_A ≤ +85°C. Typical values are at V_CC = 3.3 V, 25°C (unless otherwise noted).

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
POWER SUPPLY
V_CC	Supply voltage			3.15	3.3	3.45	V
I_CC	Supply current	OUTA_PD = 0, OUTB_PD = 1 OUTA_MUX = OUTB_MUX = 1 OUTA_PWR = 31, CPG=7 f_OSC= f_PD = 100 MHz, f_VCO = f_OUT = 14 GHz p_OUT = 3 dBm with 50-Ω resistor pullup			340		mA
	Power-on reset current	RESET=1			170
	Power-down current	POWERDOWN=1			5
OUTPUT CHARACTERISTICS
p_OUT	Single-ended output power⁽³⁾⁽⁵⁾	50-Ω resistor pullup OUTx_PWR = 50	f_OUT = 8 GHz		5		dBm
		50-Ω resistor pullup OUTx_PWR = 50	f_OUT = 15 GHz		2
		1-nH inductor pullup OUTx_PWR = 50	f_OUT = 8 GHz		10
		1-nH inductor pullup OUTx_PWR = 50	f_OUT = 15 GHz		7
Xtalk	Isolation between outputs A and B. Measured on output A	OUTA_MUX = VCO OUTB_MUX = channel divider			–50		dBc
H2	Second harmonic⁽⁵⁾	OUTA_MUX = VCO f_VCO = 8 GHz			–20		dBc
H2	Second harmonic⁽⁵⁾	OUTA_MUX = VCO f_VCO = 11 GHz			–30		dBc
H3	Third harmonic⁽⁵⁾	OUTA_MUX = VCO f_VCO = 8 GHz			–50		dBc
INPUT SIGNAL PATH
f_OSCin	Reference input frequency	OSC_2X = 0		5		1400	MHz
f_OSCin	Reference input frequency	OSC_2X = 1		5		200
v_OSCin	Reference input voltage	AC-coupled required ⁽²⁾		0.2		2	Vpp
f_MULT	Multiplier frequency (only applies when multiplier is enabled)	Input range		30		70	MHz
f_MULT		Output range		180		250	MHz
PHASE DETECTOR AND CHARGE PUMP
f_PD	Phase detector frequency⁽²⁾	Integer mode	MASH_ORDER = 0	0.125		400	MHz
		Fractional mode	MASH_ORDER= 1, 2, 3	5		300
		Fractional mode	MASH_ORDER = 4	5		240
I_CPout	Charge-pump leakage current	CPG = 0			15		nA
	Effective charge pump current. This is the sum of the up and down currents	CPG = 4			3		mA
		CPG = 1			6
		CPG = 5			9
		CPG = 3			12
		CPG = 7			15
PN_{PLL_1/f}	Normalized PLL 1/f noise	f_PD = 100 MHz, f_VCO = 12 GHz⁽⁴⁾⁽⁴⁾⁽⁴⁾⁽⁴⁾			–129		dBc/Hz
PN_{PLL_flat}	Normalized PLL noise floor	f_PD = 100 MHz, f_VCO = 12 GHz⁽⁴⁾⁽⁴⁾⁽⁴⁾⁽⁴⁾			–236		dBc/Hz
VCO CHARACTERISTICS
PN_VCO	VCO phase noise	VCO1 f_VCO = 8 GHz	10 kHz		–80		dBc/Hz
			100 kHz		–107
			1 MHz		–128
			10 MHz		–148
			90 MHz		–157
		VCO2 f_VCO = 9.2 GHz	10 kHz		–79
			100 kHz		–105
			1 MHz		–127
			10 MHz		–147
			90 MHz		–157
		VCO3 f_VCO = 10.3 GHz	10 kHz		–77
			100 kHz		–104
			1 MHz		–126
			10 MHz		–147
			90 MHz		–157
		VCO4 f_VCO = 11.3 GHz	10 kHz		–76
			100 kHz		–103
			1 MHz		–125
			10 MHz		–145
			90 MHz		–158
		VCO5 f_VCO = 12.5 GHz	10 kHz		–74
			100 kHz		–100
			1 MHz		–123
			10 MHz		–144
			90 MHz		–157
		VCO6 f_VCO = 13.3 GHz	10 kHz		–73
			100 kHz		–100
			1 MHz		–122
			10 MHz		–143
			90 MHz		–155
		VCO7 f_VCO = 14.5 GHz	10 kHz		–73
			100 kHz		–99
			1 MHz		–121
			10 MHz		–143
			90 MHz		–152
t_VCOCAL	VCO calibration speed	Switch across the entire frequency band f_OSC = 200 MHz, f_PD = 100 MHz⁽¹⁾	No assist		50		µs
			Partial assist		35
			Close frequency		20
			Full assist		5
K_VCO	VCO gain	8 GHz			92		MHz/V
		9.2 GHz			91
		10.3 GHz			115
		11.3 GHz			121
		12.5 GHz			195
		13.3 GHz			190
		14.5 GHz			213
\|ΔT_CL\|	Allowable temperature drift when VCO is not recalibrated	RAMP_EN = 0 or RAMP_MANUAL= 1			125		°C
H2	VCO second harmonic	f_VCO = 8 GHz, divider disabled			–20		dBc
H3	VCO third haromonic	f_VCO = 8 GHz, divider disabled			–50		dBc
SYNC PIN AND PHASE ALIGNMENT
f_OSCinSYNC	Maximum usable OSCin with sync pin (Figure 27)	Category 3		0		100	MHz
f_OSCinSYNC	Maximum usable OSCin with sync pin (Figure 27)	Categories1 and 2		0		1400	MHz
DIGITAL INTERFACE Applies to SLK, SDI, CSB, CE, RampDir, RampClk, MUXout, SYNC (CMOS Mode), SysRefReq (CMOS Mode)
V_IH	High-level input voltage			1.4		Vcc	V
V_IL	Low-level input voltage			0		0.4	V
I_IH	High-level input current			–25		25	µA
I_IL	Low-level input current			–25		25	µA
V_OH	High-level output voltage	MUXout pin	Load current = –10 mA	V_CC – 0.4			V
V_OL	Low-level output voltage	MUXout pin	Load current = 10 mA			0.4	V

(1) See Application and Implementation for more details on the different VCO calibration modes.

(2) For lower VCO frequencies, the N divider minimum value can limit the phase-detector frequency.

(3) Single ended output power obtained after de-embedding microstrip trace losses and matching with a manual tuner. Unused port terminated to 50 ohm load.

(4) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat components. PLL_flat = PLL_FOM + 20 × log(Fvco/Fpd) + 10 × log(Fpd / 1Hz). PLL_flicker (offset) = PLL_flicker_Norm + 20 × log(Fvco / 1GHz) – 10 × log(offset / 10kHz). Once these two components are found, the total PLL noise can be calculated as PLL_Noise = 10 × log(10 ^{PLL_Flat / 10} + 10 ^{PLL_flicker / 10} )

(5) Output power, spurs, and harmonics can vary based on board layout and components.