7.3.2 Enable and UVLO

Using a resistor divider from VIN to EN as shown in the schematic diagram below, the input voltage at which the part begins switching can be increased above the normal input UVLO level according to

Equation 1.

For example, suppose that the required input UVLO level is 3.69 V. Choosing R_enb = 10 kΩ, then we calculate R_ent = 20 kΩ.

Figure 16. Setting Enable and UVLO

Alternatively, the EN pin can be driven from another voltage source to cater to system sequencing requirements commonly found in FPGA and other multi-rail applications. Figure 17 shows an LMZ10503 that is sequenced to start based on the voltage level of a master system rail (V_OUT1).

Figure 17. Setting Enable and UVLO Using External Power Supply