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ZHCSDO6B May 2015 – September 2020 MSP430FG6425 , MSP430FG6426 , MSP430FG6625 , MSP430FG6626

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机械数据 (封装 | 引脚)

PZ|100
- MTQF013A

散热焊盘机械数据 (封装 | 引脚)

PZ|100
- QFND428

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8.8.13.1 12-Bit DAC, Supply Specifications

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER		TEST CONDITIONS	V_CC	MIN	TYP	MAX	UNIT
AV_CC	Analog supply voltage	AV_CC = DV_CC, AV_SS = DV_SS = 0 V		2.2		3.6	V
I_DD	Supply current, single DAC channel⁽¹⁾ ⁽²⁾	DAC12AMPx = 2, DAC12IR = 0, DAC12OG = 1, DAC12_xDAT = 0800h, VeREF+ = VREFBG = 1.16 V	3 V		65	110	µA
		DAC12AMPx = 2, DAC12IR = 1, DAC12_xDAT = 0800h, VeREF+ = AV_CC	2.2 V to 3.6 V		125	165
		DAC12AMPx = 5, DAC12IR = 1, DAC12_xDAT = 0800h, VeREF+ = AV_CC			250	350
		DAC12AMPx = 7, DAC12IR = 1, DAC12_xDAT = 0800h, VeREF+ = AV_CC			750	1100
PSRR	Power supply rejection ratio⁽³⁾ ⁽⁴⁾	DAC12_xDAT = 800h, VeREF+ = 1.16 V or 1.5 V, ΔAV_CC = 100 mV	2.2 V to 3.6 V		70		dB
PSRR	Power supply rejection ratio⁽³⁾ ⁽⁴⁾	DAC12_xDAT = 800h, VeREF+ = 1.16 V or 2.5 V ΔAV_CC = 100 mV	3 V		70		dB

(1) No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.

(2) Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications Section 8.8.13.4.

(3) PSRR = 20 log (ΔAV_CC / ΔV_{DAC12_xOUT})

(4) The internal reference is not used.

Figure 8-19 Linearity Test Load Conditions, Gain and Offset Definition

Section 8.8.13.2 lists the linearity specifications of the DAC.