ZHCSH08 October 2017 MSP432E411Y
PRODUCTION DATA.
Hitachi mode is an asynchronous mode that does not use an external LCDMCLK and allows for full programmability of the read and write strobes, data, and enables through the LIDDCS0CFG register. In addition to the parameter delays configured in the LIDDCS0CFG register, the delay times in the following figures that are from the internal MCLK to the signal output must be added to the programmed delays for full timing information. All of the parameter values associated with the following figures can be found in Table 5-56 and Table 5-57.
In Figure 5-48, Figure 5-49, and Figure 5-50 the second LCDMCLK is shown as E1 and can be used as the enable strobe for a second display in Hitachi mode. The primary enable strobe is the LCDAC signal.
NOTE
The acronyms WRSU, WRDUR, WRHOLD, and GAP in the following figures correspond to the bit fields of the LIDDCS0CFG register described in Section 5.15.16.1.