The OPAx607 devices feature a Power Down mode for power critical applications. Under logic control, the amplifier can be switched from normal operation (consuming ≤ 1 mA) to a Power Down current of less than 1 µA. When the PD pin is connected high, the amplifier is active. Connecting the PD pin to logic low disables the amplifier and places the output in a high-impedance state. The output of an op amp is high impedance similar to a tri-state high-impedance gate under a Power Down condition; however, the feedback network behaves as a parallel load.

If the Power Down mode is not used, connect PD to the positive supply pin or leave floating. See the Power Down (Device Enabled When Floating) section in Section 7.5 table for the enable and disable threshold voltages. The PD pin can be left floating to keep the op amp always enabled, which is primarily possible because of the presence of an internal pullup resistor within the op amp that, by default, always keeps the PD pin weakly tied to V_S+. However it is also acceptable to strengthen the pull up from the PD pin by connecting a low value resistance from the PD pin to V_S+. This helps make the part less susceptible to noise and transient pick up on the PD pin. Looking at the PD pin bias current in Figure 7-21 can help us get an accurate understanding of the voltage required to be applied on the PD pin for enabling and powering down. Note: the hysteresis present in Figure 7-21 help with single shot power up and power down of OPAx607 devices.

The PD pin exhibits a special type of ESD protection which allows users to apply any voltage between V_S– to 6 V irrespective of the voltage at the V_S+. Special ESD structure at the PD pin helps in relaxing the requirements on power sequencing during power up and power down condition. Refer to Figure 8-4 for details of the internal ESD structure. The absolute voltage limits applicable on PD pin can be found in Section 7.1 table. Another key care about in PD condition is to ensure the IN+ and IN– are not exposed to a high differential voltage continuously. In a power up condition the op-amp's loop gain ensure the IN+ pin and the IN– track each other closely. However in PD condition the op-amp is inactive and IN– will be usually weakly tied to GND through the R_G resistor. Exposing the IN+ pin continuously to a high voltage in such a condition will result in irreversible offset voltage (V_OS) shift.