9.1.4.1 Setting Resistor Values to Minimize Noise

The OPA657 provides a very low input noise voltage while requiring a low 14 mA of quiescent current. To take full advantage of this low input noise, careful attention to the other possible noise contributors is required. Figure 33 shows the operational amplifier noise analysis model with all the noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms in either nV/√Hz or pA/√Hz.

Figure 33. Operational Amplifier Noise Analysis Model

The total output spot noise voltage can be computed as the square root of the squared contributing terms to the output noise voltage. This computation is adding all the contributing noise powers at the output by superposition, then taking the square root to get back to a spot noise voltage. Equation 5 shows the general form for this output noise voltage using the terms shown in Figure 28:

Equation 5.

Dividing this expression by the noise gain (G_N = 1 + R_F/R_G) gives the equivalent input referred spot noise voltage at the noninverting input, as shown in Equation 6:

Equation 6.

Putting high resistor values into Equation 6 can quickly dominate the total equivalent input referred noise. A source impedance on the noninverting input of 1.6 kΩ adds a Johnson voltage noise term equal to just that for the amplifier itself (5 nV/√Hz). While the JFET input of the OPA657 is ideal for high source impedance applications, both the overall bandwidth and noise may be limited by these higher source impedances in the noninverting configuration of Figure 29.

9.1.4.2 Frequency Response Control

Voltage-feedback operational amplifiers exhibit decreasing closed-loop bandwidth as the signal gain is increased. In theory, this relationship is described by the gain bandwidth product (GBP) shown in the Electrical Characteristics: VS = ±5 V. Ideally, dividing GBP by the noninverting signal gain (also called the noise gain, or NG) predicts the closed-loop bandwidth. In practice, this only holds true when the phase margin approaches 90°, as it does in high-gain configurations. At low gains (increased feedback factors), most high-speed amplifiers exhibit a more complex response with lower phase margin. The OPA657 is compensated to give a maximally-flat, second-order, Butterworth, closed-loop response at a noninverting gain of +10 V/V (see Figure 29). This results in a typical gain of +10-V/V bandwidth of 275 MHz, far exceeding that predicted by dividing the 1600-MHz GBP by 10. Increasing the gain causes the phase margin to approach 90° and the bandwidth to more closely approach the predicted value of (GBP/NG). At a gain of +50 V/V the OPA657 shows the 32-MHz bandwidth predicted using the simple formula and the typical GBP of 1600 MHz. Inverting operation offers some interesting opportunities to increase the available gain-bandwidth product. When the source impedance is matched by the gain resistor (see Figure 30), the signal gain is –(R_F/R_G) while the noise gain for bandwidth purposes is (1 + R_F/R_G). This cuts the noise gain in half, increasing the minimum stable gain for inverting operation under these conditions to –12 V/V and the equivalent gain bandwidth product to 3.2 GHz.

9.1.4.3 Driving Capacitive Loads

One of the most demanding and yet very common load conditions for an operational amplifier is capacitive loading. Often, the capacitive load is the input of an ADC—including additional external capacitance which may be recommended to improve A/D linearity. A high-speed, high open-loop gain amplifier such as the OPA657 can be very susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the signal path that can decrease the phase margin. Several external solutions to this problem have been suggested. When the primary considerations are frequency response flatness, pulse response fidelity, and/or distortion, the simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series isolation resistor between the amplifier output and the capacitive load. This does not eliminate the pole from the loop response, but rather shifts it and adds a zero at a higher frequency. The additional zero acts to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving stability.

The Typical Characteristics illustrate the Recommended R_S vs Capacitive Load (Figure 17) and the resulting frequency response at the load. In this case, a design target of a maximally-flat frequency response is used. Lower values of R_S may be used if some peaking can be tolerated. Also, operating at higher gains (than the +10 V/V used in the Typical Characteristics) require lower values of R_S for a minimally-peaked frequency response. Parasitic capacitive loads greater than 2 pF can begin to degrade the performance of the OPA657. Long PC board traces, unmatched cables, and connections to multiple devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the recommended series resistor as close as possible to the OPA657 output pin (see the Layout Guidelines section).

9.1.4.4 Distortion Performance

The OPA657 is capable of delivering a low-distortion signal at high frequencies over a wide range of gains. The distortion plots in the Typical Characteristics: VS = ±5 V show the typical distortion under a wide variety of conditions.

Generally, until the fundamental signal reaches very high frequencies or powers, the second-harmonic dominates the distortion with a negligible third-harmonic component. Focusing then on the second-harmonic, increasing the load impedance improves distortion directly. Remember that the total load includes the feedback network—in the noninverting configuration this is sum of R_F + R_G, while in the inverting configuration this is just R_F (see Figure 29). Increasing output voltage swing increases harmonic distortion directly. A 6-dB increase in output swing generally increases the second-harmonic 12 dB and the third-harmonic 18 dB. Increasing the signal gain also increases the second-harmonic distortion. Again, a 6-dB increase in gain increases the second- and third-harmonic by approximately 6 dB, even with a constant output power and frequency. And finally, the distortion increases as the fundamental frequency increases due to the roll-off in the loop gain with frequency. Conversely, the distortion improves going to lower frequencies down to the dominant open-loop pole at approximately 100 kHz. Starting from the –70-dBc second-harmonic for a 5-MHz, 2 V_PP fundamental into a 200-Ω load at G = +10 V/V (from the Typical Characteristics: VS = ±5 V), the second-harmonic distortion for frequencies lower than 100 kHz is approximately less than –90 dBc.

The OPA657 has an extremely low third-order harmonic distortion. This also shows up in the two-tone, third-order, intermodulation spurious (IM3) response curves. The third-order spurious levels are extremely low (< –80 dBc) at low output power levels. The output stage continues to hold them low even as the fundamental power reaches higher levels. As shown in Typical Characteristics: VS = ±5 V, the spurious intermodulation powers do not increase as predicted by a traditional intercept model. As the fundamental power level increases, the dynamic range does not decrease significantly. For two tones centered at 10 MHz, with 4 dBm/tone into a matched 50-Ω load (that is, 1 V_PP for each tone at the load, which requires 4 V_PP for the overall two-tone envelope at the output pin), the Typical Characteristics: VS = ±5 V show a 82-dBc difference between the test tone and the third-order intermodulation spurious levels. This exceptional performance improves further when operating at lower frequencies and/or higher load impedances.

9.1.4.5 DC Accuracy and Offset Control

The OPA657 can provide excellent DC accuracy due to its high open-loop gain, high common-mode rejection, high power-supply rejection, and its trimmed input offset voltage (and drift) along with the negligible errors introduced by the low input bias current. For the best DC precision, a high-grade version (OPA657UB or OPA657NB) screens the key DC parameters to an even tighter limit. Both standard- and high-grade versions take advantage of a new final test technique to 100% test input offset voltage drift over temperature. This discussion uses the high-grade typical and min/max Electrical Characteristics: VS = ±5 V for illustration; however, an identical analysis applies to the standard-grade version.

The total output DC offset voltage in any configuration and temperature is the combination of a number of possible error terms. In a JFET part such as the OPA657, the input bias current terms are typically quite low but are unmatched. Using bias-current cancellation techniques, more typical in bipolar input amplifiers, does not improve output DC offset errors. Errors due to the input bias current only become dominant at elevated temperatures. The OPA657 shows the typical 2× increase in every 10°C common to JFET-input stage amplifiers. Using the 5-pA maximum tested value at +25°C, and a +20°C internal self heating (see thermal analysis), the maximum input bias current at +85°C ambient is 5 pA × 2^{(105 – 25)/10} = 1280 pA. For noninverting configurations, this term only begins to be a significant term versus the input offset voltage for source impedances greater than 750 kΩ. This would also be the feedback resistor value for transimpedance applications (see Figure 34) where the output DC error due to inverting input bias current is on the order of that contributed by the input offset voltage. In general, except for these extremely high-impedance values, the output DC errors due to the input bias current may be neglected.

After the input offset voltage itself, the most significant term contributing to output offset voltage is the PSRR for the negative supply. This term is modeled as an input offset voltage shift due to changes in the negative power-supply voltage (and similarly for the +PSRR). The high-grade test limit for –PSRR is 68 dB. This translates into 0.4-mV/V input offset voltage shift = 10^(–68/20). This low sensitivity to the negative supply voltage requires a 1.5-V change in the negative supply to match the ±0.6mV input offset voltage error. The +PSRR is tested to a minimum value of 78 dB. This translates into 10^(–78/20) = 0.125 mV/V sensitivity for the input offset voltage to positive power-supply changes.

As an example, compute the worst-case output DC error for the transimpedance circuit of Figure 34 at 25°C and then the shift over the 0°C to 70°C range given the following assumptions.

Negative Power Supply

= –5 V ±0.2 V with a ±5 mV/°C worst-case shift

Positive Power Supply

= +5 V ±0.2 V with a ±5 mV/°C worst-case shift

Initial 25°C Output DC Error Band

= ±0.6 mV (OPA657 high-grade input offset voltage limit)

±0.08 mV (due to the –PSRR = 0.4 mV/V × ±0.2 V)

±0.04 mV (due to the +PSRR = 0.2 mV/V × ±0.2 V)

Total = ±0.72mV

This would be the worst-case error band in volume production at 25°C acceptance testing given the conditions stated. Over the temperature range (0°C to 70°C), expect the following worst-case shifting from initial value. A 20°C internal junction self-heating is assumed here.

±0.36 mV (OPA657 high-grade input offset drift)

= ±6 μV/°C × (70°C + 20°C – 25°C)

±0.11 mV (–PSRR of 66dB with 5mV × (70°C – 25°C) supply shift)

±0.04 mV (+PSRR of 76dB with 5mV × (70°C – 25°C) supply shift)

Total = ±0.51mV

This would be the worst-case shift from an initial offset over a 0°C to 70°C ambient for the conditions stated. Typical initial output DC error bands and shifts over temperature are much lower than these worst-case estimates.

In the transimpedance configuration, the CMRR errors can be neglected because the input common-mode voltage is held at ground. For noninverting gain configurations (see Figure 29), the CMRR term needs to be considered but is typically far lower than the input offset voltage term. With a tested minimum of 91 dB (28 μV/V), the added apparent DC error is no more than ±0.06 mV for a ±2-V input swing to the circuit of Figure 29.

Table 1. Design Requirements