米6体育平台手机版

ZHCSK40E August 2019 – August 2024 OPA810

PRODUCTION DATA

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

D|8
DBV|5
DCK|5

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.7 Electrical Characteristics: 5 V

at T_A = 25°C, V_S+ = 5 V, V_S– = 0 V, common-mode voltage (V_CM) = 1.25 V, and R_L = 1 kΩ connected to 1.25 V⁽¹⁾ (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT	Test Level⁽²⁾
AC PERFORMANCE
SSBW	Small-signal bandwidth	G = 1, V_o = 20 mV_PP, R_F = 0 Ω		133		MHz	C
		G = 1, V_o = 20 mV_PP, R_F= 0 Ω, C_L= 10 pF		135			C
		G = –1, V_o = 20 mV_PP		65			C
LSBW	Large-signal bandwidth	G = 2 V_o = 2 V_PP		36		MHz	C
GBWP	Gain-bandwidth product			70		MHz	C
	Bandwidth for 0.1-dB flatness	G = 2, V_o = 20 mV_PP		16		MHz	C
SR	Slew rate (20%-80%)⁽³⁾	G = 2, V_o = –1-V to 1-V step		134		V/µs	C
SR	Slew rate (20%-80%)⁽³⁾	G = 2, V_o = –2-V to 2-V step, V_S = ±2.5 V		78		V/µs	C
	Rise time	V_o = 200-mV step		4		ns	C
	Fall time	V_o = 200-mV step		4		ns	C
	Settling time to 0.1%	G = 2, V_o = –2-V to 0-V step, V_S = ±2.5 V		100		ns	C
	Settling time to 0.001%	G = 2, V_o = –2-V to 0-V step, V_S = ±2.5 V		565		ns	C
	Input overdrive recovery	G = 1, (V_S– – 0.5 V) to (V_S+ + 0.5 V) input, V_S = ±2.5 V		76		ns	C
	Output overdrive recovery	G = –1, (V_S– – 0.5 V) to (V_S+ + 0.5 V) input, V_S = ±2.5 V		93		ns	C
HD2	Second-order harmonic distortion	f = 100 kHz, R_L = 1 kΩ, V_o = 2 V_PP		–102		dBc	C
HD2	Second-order harmonic distortion	f = 1 MHz, R_L = 1 kΩ, V_o = 2 V_PP		–81		dBc	C
HD3	Third-order harmonic distortion	f = 100 kHz, R_L = 1 kΩ, V_o = 2 V_PP		–114		dBc	C
HD3	Third-order harmonic distortion	f = 1 MHz, R_L = 1 kΩ, V_o = 2 V_PP		–92		dBc	C
e_n	Input-referred voltage noise	Flat-band, 1/f corner at 1.5 kHz		6.3		nV/√Hz	C
i_n	Input-referred current noise	f = 10 kHz		5		fA/√Hz	C
z_O	Closed-loop output impedance	f = 100 kHz		0.007		Ω	C
DC PERFORMANCE
A_OL	Open-loop voltage gain	f = dc, V_o = 1.25 V to 3.25 V	104	118		dB	A
V_OS	Input offset voltage	SOIC package		100	550	µV	A
V_OS	Input offset voltage	DBV and DCK packages		100	760	µV	A
	Input offset voltage drift	T_A = –40°C to +125°C		2.5	10	µV/°C	B
	Input bias current			2	20	pA	A
	Input offset current			1	20	pA	A
CMRR	Common-mode rejection ratio	f = dc, V_CM = 0.75 V to 1.75 V, SOIC package	73	92		dB	A
CMRR	Common-mode rejection ratio	T_A = –40°C to +125°C, SOIC package	73			dB	B
INPUT
	Allowable input differential voltage	See Figure 6-54		±5		V	C
	Common-mode input impedance	In closed-loop configuration		12 \|\| 2.5		GΩ\|\|pF	C
	Differential input capacitance	In open-loop configuration		0.5		pF	C
	Most positive input voltage	ΔV_OS < 5 mV⁽⁴⁾	V_S+ + 0.2	V_S+ + 0.3		V	A
	Most negative input voltage	ΔV_OS < 5 mV⁽⁴⁾	V_S- – 0.2	V_S- – 0.3		V	A
	Most positive input voltage for main-JFET stage	See Figure 6-41	V_S+ – 2.9	V_S+ – 2.5		V	C
OUTPUT
V_OCRH	Output voltage range high	R_L = 667 Ω	V_S+ – 0.12	V_S+ – 0.09		V	A
V_OCRH	Output voltage range high	T_A = –40°C to +125°C, R_LOAD = 667 Ω	V_S+ – 0.15			V	B
V_OCRL	Output voltage range low	R_L = 667 Ω		V_S–+ 0.06	V_S– + 0.11	V	A
V_OCRL	Output voltage range low	T_A = –40°C to +125°C, R_L = 667 Ω			V_S– + 0.15	V	B
I_O(max)	Linear output drive (sourcing and sinking)	V_O = 1.4 V, R_L = 27.5 Ω, ΔV_OS < 1 mV, V_S+ = 3 V and V_S– = –2 V	50	64		mA	A
I_SC	Output short-circuit current			96		mA	B
C_L	Capacitive load drive	< 3-dB peaking, R_S = 0 Ω		10		pF	C
POWER SUPPLY
I_Q	Quiescent current per channel		3.15	3.7	4.5	mA	A
PSRR	Power-supply rejection ratio	ΔV_S = ±0.5 V⁽⁵⁾, SOIC package	78	100		dB	A
PSRR	Power-supply rejection ratio	T_A = –40°C to +125°C, SOIC package	78			dB	B
AUXILIARY CMOS INPUT STAGE
	Gain-bandwidth product			27		MHz	C
	Input-referred voltage noise	f = 1 MHz		20		nV/√Hz	C
	Input offset voltage	V_CM = V_S+ – 1.5 V, no load, SOIC package			1.6	mV	A
	Input bias current	V_CM = V_S+ – 1.5 V		2	20	pA	A

(1) For ac specifications, V_S+ = 3.5 V, V_S– = –1.5 V, G = 2 V/V, R_F = 1 kΩ, C_L = 4.7 pF, V_CM = 0 V (unless otherwise noted).

(2) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.

(3) Lower of the measured positive and negative slew rate.

(4) Change in input offset from the value when input is biased to 0 V.

(5) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to +PSRR and –PSRR.