米6体育平台手机版

ZHCSK40E August 2019 – August 2024 OPA810

PRODUCTION DATA

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

D|8
DBV|5
DCK|5

散热焊盘机械数据 (封装 | 引脚)

订购信息

6.5 Electrical Characteristics: 10 V

at T_A = 25°C, V_S+ = 5 V, V_S– = –5 V, common-mode voltage (V_CM) = mid-supply, and R_L = 1 kΩ connected to mid-supply⁽¹⁾ (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT	TEST LEVEL⁽²⁾
AC PERFORMANCE
SSBW	Small-signal bandwidth	G = 1, V_O = 20 mV_PP, R_F = 0 Ω		135		MHz	C
		G = 1, V_O = 20 mV_PP, R_F = 0 Ω, C_L= 10 pF		140			C
		G = –1, V_O = 20 mV_PP		68			C
LSBW	Large-signal bandwidth	G = 2, V_O = 2 V_PP		41		MHz	C
GBWP	Gain-bandwidth product			70		MHz	C
	Bandwidth for 0.1-dB flatness	G = 2, V_O = 20 mV_PP		16		MHz	C
SR	Slew rate (20%-80%)⁽³⁾	G = 2, V_O = –2-V to 2-V step		200		V/µs	C
	Rise time	V_O = 200-mV step		4		ns	C
	Fall time	V_O = 200-mV step		4		ns	C
	Settling time to 0.1%	G = 2, V_O = 2-V step		47		ns	C
	Settling time to 0.1%	G = 2, V_O = 8-V step		65		ns	C
	Settling time to 0.001%	G = 2, V_O = 2-V step		330		ns	C
	Settling time to 0.001%	G = 2, V_O = 8-V step		230		ns	C
	Input overdrive recovery	G = 1, R_F = 0 Ω, (V_S– – 0.5 V) to (V_S+ + 0.5 V) input		55		ns	C
	Output overdrive recovery	G = –1, (V_S– – 0.5 V) to (V_S+ + 0.5 V) input		55		ns	C
HD2	Second-order harmonic distortion	f = 100 kHz, R_L = 1 kΩ, V_O = 2 V_PP		–120		dBc	C
HD2	Second-order harmonic distortion	f = 1 MHz, R_L= 1 kΩ, V_O = 2 V_PP		–101		dBc	C
HD3	Third-order harmonic distortion	f = 100 kHz, R_L= 1 kΩ, V_O = 2 V_PP		–137		dBc	C
HD3	Third-order harmonic distortion	f = 1 MHz, R_L= 1 kΩ, V_O = 2 V_PP		–101		dBc	C
e_n	Input-referred voltage noise	Flat-band, 1/f corner at 1.5 kHz		6.3		nV/√Hz	C
i_n	Input-referred current noise	f = 10 kHz		5		fA/√Hz	C
z_O	Closed-loop output impedance	f = 100 kHz		0.007		Ω	C
DC PERFORMANCE
A_OL	Open-loop voltage gain	f = dc, V_O = ±2.5 V	108	120		dB	A
V_OS	Input offset voltage	SOIC package		100	500	µV	A
V_OS	Input offset voltage	DBV and DCK packages		100	715	µV	A
	Input offset voltage drift	T_A = –40°C to +125°C		2.5	10	µV/°C	B
	Input bias current			2	20	pA	A
	Input offset current			1	20	pA	A
CMRR	Common-mode rejection ratio	f = dc, V_CM = –3 V to 1 V, SOIC package	80	100		dB	A
CMRR	Common-mode rejection ratio	T_A = –40°C to +125°C, SOIC package	80			dB	B
INPUT
	Allowable input differential voltage	See Figure 6-54		±7		V	C
	Common-mode input impedance	In closed-loop configuration		12 \|\| 2		GΩ\|\|pF	C
	Differential input capacitance	In open-loop configuration		0.5		pF	C
	Most positive input voltage	ΔV_OS < 5 mV⁽⁴⁾	V_S+ + 0.2	V_S+ + 0.3		V	A
	Most negative input voltage	ΔV_OS < 5 mV⁽⁴⁾	V_S– – 0.2	V_S– – 0.3		V	A
	Most positive input voltage for main-JFET stage	See Figure 6-17	V_S+ – 2.9	V_S+ – 2.5		V	C
OUTPUT
V_OCRH	Output voltage range high	R_L = 667 Ω	V_S+ – 0.18	V_S+ – 0.11		V	A
V_OCRH	Output voltage range high	T_A = –40°C to +125°C, R_L = 667 Ω	V_S+ – 0.2			V	B
V_OCRL	Output voltage range low	R_L = 667 Ω		V_S– + 0.08	V_S– + 0.15	V	A
V_OCRL	Output voltage range low	T_A = –40°C to +125°C, R_L = 667 Ω			V_S– + 0.2	V	B
I_O(max)	Linear output drive (sourcing and sinking)	V_O = 2.65 V, R_L = 51 Ω, ΔV_OS < 1 mV	52	75		mA	A
I_SC	Output short-circuit current			100		mA	B
C_L	Capacitive load drive	< 3-dB peaking, R_S = 0 Ω		10		pF	C
POWER SUPPLY
I_Q	Quiescent current per channel			3.7	4.6	mA	A
PSRR	Power-supply rejection ratio	ΔV_S = ±2 V⁽⁵⁾, SOIC package	79	100		dB	A
PSRR	Power-supply rejection ratio	T_A = –40°C to +125°C, SOIC package	79			dB	B
AUXILIARY CMOS INPUT STAGE
	Gain-bandwidth product			27		MHz	C
	Input-referred voltage noise	f = 1 MHz		20		nV/√Hz	C
	Input offset voltage	V_CM = V_S+ – 1.5 V, no load, SOIC package			1.6	mV	A
	Input bias current	V_CM = V_S+ – 1.5 V		2	20	pA	A

(1) For ac specifications, G = 2 V/V, R_F = 1 kΩ and C_L = 4.7 pF (unless otherwise noted).

(2) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.

(3) Lower of the measured positive and negative slew rate.

(4) Change in input offset from the value when input is biased to midsupply.

(5) Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to +PSRR and –PSRR.