ZHCSJ41 December   2018 SN55HVD233-SEP

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Driver Electrical Characteristics
    6. 7.6  Receiver Electrical Characteristics
    7. 7.7  Driver Switching Characteristics
    8. 7.8  Receiver Switching Characteristics
    9. 7.9  Device Switching Characteristics
    10. 7.10 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Modes
      2. 9.3.2 Loopback
      3. 9.3.3 CAN Bus States
      4. 9.3.4 ISO 11898 Compliance of SN55HVD233-SEP
        1. 9.3.4.1 Introduction
        2. 9.3.4.2 Differential Signal
          1. 9.3.4.2.1 Common-Mode Signal
        3. 9.3.4.3 Interoperability of 3.3-V CAN in 5-V CAN Systems
      5. 9.3.5 Thermal Shutdown
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Diagnostic Loopback
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Slope Control
        2. 10.2.2.2 Standby
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Bus Loading, Length, and Number of Nodes
      2. 12.1.2 CAN Termination
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 接收文档更新通知
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 术语表
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6 Receiver Electrical Characteristics

At TA = –55°C to 125°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIT+ Positive-going input threshold voltage V(LBK) = 0 V, see Table 1 750 900 mV
VIT– Negative-going input threshold voltage 500 650 mV
Vhys Hysteresis voltage (VIT+ – VIT–) 100 mV
VOH High-level output voltage IO = –4 mA, see Figure 17 2.4 V
VOL Low-level output voltage IO = 4 mA, see Figure 17 0.4 V
II Bus input current V(CANH) or V(CANL) = 12 V Other bus pin = 0 V,
V(D) = 3 V,
V(LBK) = 0 V,
V(RS) = 0 V		 150 500 µA
V(CANH) or V(CANL) = 12 V,
VCC = 0 V		 150 600
CANH or CANL = –7 V –610 –100
CANH or CANL = –7 V,
VCC = 0 V		 –450 –100
CI Input capacitance (CANH or CANL) Pin-to-ground, VI = 0.4 sin(4E6πt) + 0.5 V,
V(D) = 3 V, V(LBK) = 0 V		 40 pF
CID Differential input capacitance Pin-to-pin, VI = 0.4 sin(4E6πt) + 0.5 V,
V(D) = 3 V, V(LBK) = 0 V 		20 pF
RID Differential input resistance V(D) = 3 V, V(LBK) = 0 V 40 105 kΩ
RIN Input resistance (CANH or CANL) 20 55 kΩ
ICC Supply current Standby V(RS) = VCC, V(D) = VCC, V(LBK) = 0 V 200 700 µA
Dominant V(D) = 0 V, no load, V(RS) = 0 V, V(LBK) = 0 V 6 mA
Recessive V(D) = VCC, no load, V(RS) = 0 V, V(LBK) = 0 V 6 mA
(1) All typical values are at 25°C and with a 3.3-V supply.
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