米6体育平台手机版

ZHCS686A January 2012 – March 2016 SN65LVCP114

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

ZJA|167
- MPBGA19

散热焊盘机械数据 (封装 | 引脚)

订购信息

6 Pin Configuration and Functions

ZJA Package

167-Pin NFBGA

Top View

Pin Functions

PIN		DIRECTION TYPE SUPPLY	DESCRIPTION
NAME	BALLS	DIRECTION TYPE SUPPLY	DESCRIPTION
LINE-SIDE HIGH-SPEED I/O
CINP0 CINN0	A12 A13	Input (with 50-Ω termination to input common mode)	Differential input, lane 0 line side.
CINP1 CINN1	A9 A10	Input (with 50-Ω termination to input common mode)	Differential input, lane 1 line side
CINP2 CINN2	A6 A7	Input (with 50-Ω termination to input common mode)	Differential input, lane 2 line side
CINP3 CINN3	A3 A4	Input (with 50-Ω termination to input common mode)	Differential input, lane 3 line side
COUTP0 COUTN0	C11 C12	Output	Differential output, lane 0 line side
COUTP1 COUTN1	C8 C9	Output	Differential output, lane 1 line side
COUTP2 COUTN2	C5 C6	Output	Differential output, lane 2 line side
COUTP3 COUTN3	C2 C3	Output	Differential output, lane 3 line side
SWITCH-SIDE HIGH-SPEED I/O
AINP0 AINN0	F14G14	Input (with 50-Ω termination to input common mode)	Differential input, lane 0, fabric switch_A_side
AINP1 AINN1	J14 K14	Input (with 50-Ω termination to input common mode)	Differential input, lane 1, fabric switch_A_side
AINP2 AINN2	P12 P11	Input (with 50-Ω termination to input common mode)	Differential input, lane 2, fabric switch_A_side
AINP3 AINN3	P9 P8	Input (with 50-Ω termination to input common mode)	Differential input, lane 3, fabric switch_A_side
BINP0 BINN0	P6 P5	Input (with 50-Ω termination to input common mode)	Differential input, lane 0, fabric switch_B_side
BINP1 BINN1	P3 P2	Input (with 50-Ω termination to input common mode)	Differential input, lane 1, fabric switch_B_side
BINP2 BINN2	J1 H1	Input (with 50-Ω termination to input common mode)	Differential input, lane 2, fabric switch_B_side
BINP3 BINN3	F1 E1	Input (with 50-Ω termination to input common mode)	Differential input, lane 3, fabric switch_B_side
AOUTP0 AOUTN0	E12 F12	Output	Differential output, lane 0, fabric switch_A_side
AOUTP1 AOUTN1	H12 J12	Output	Differential output, lane 1, fabric switch_A_side
AOUTP2 AOUTN2	M13 M12	Output	Differential output, lane 2, fabric switch_A_side
AOUTP3 AOUTN3	M10 M9	Output	Differential output, lane 3, fabric switch_A_side
BOUTP0 BOUTN0	M7 M6	Output	Differential output, lane 0, fabric switch_B_side
BOUTP1 BOUTN1	M4 M3	Output	Differential output, lane 1, fabric switch_B_side
BOUTP2 BOUTN2	K3 J3	Output	Differential output, lane 2, fabric switch_B_side
BOUTP3 BOUTN3	G3 F3	Output	Differential output, lane 3, fabric switch_B_side
CONTROL SIGNALS
ADD0/EQA1 ADD1/EQB1 ADD2/EQC1	A14 B14 A1	Input, 2.5-V or 3.3-V CMOS - 3-state	GPIO mode EQ control pins. EQA1 and EQA0 pins are 3-state and control the EQ gain of port A. EQ control pins. EQB1 and EQB0 pins are 3-state and control the EQ gain of port B. EQ control pins. EQC1 and EQC0 pins are 3-state and control the EQ gain of port C. Refer to Table 5 for detailed information about equalization.	I²C mode ADD0 along with pins ADD1 and ADD2 comprise the three bits of the I²C slave address.
EQA0 EQB0 EQC0	D3 K1 C14	Input, 2.5-V or 3.3-V CMOS - 3-state	GPIO mode EQ control pins. EQA1 and EQA0 pins are 3-state and control theEQ gain of port A. EQ control pins. EQB1 and EQB0 pins are 3-state and control theEQ gain of port B. EQ control pins. EQC1 and EQC0 pins are 3-state and control theEQ gain of port C. Refer to Table 5 for detailed information about equalization.	I²C mode No action needed
LPA LPB LPC	P14 N14 M14	Input (with 48-kΩ pulldown) 2.5-V or 3.3-V CMOS	GPIO mode LPx enables loopback for port x HIGH: Loopback enabled LOW: Loopback disabled See Table 2 and Figure 14	I²C mode No action needed
SEL0 SEL1 SEL2 SEL3	P1 N1 M1 L1	Input (with 48-kΩ pulldown) 2.5-V or 3.3-V CMOS	GPIO mode SELx, A or B switch control for lane x HIGH: port B is selected LOW: port A is selected See Table 2	I²C mode No action needed
REXT	P13	Input, analog	External bias resistor, 1,200 Ω to ground
CS	C13	Input (with 48-kΩ pulldown) 2.5-V or 3.3-V CMOS	GPIO mode No action needed	I²C mode HIGH: acts as chip select LOW: disables I²C interface
PWDn	E14	Input (with 48-kΩ pullup) 2.5-V or 3.3-V CMOS	LOW: Powers down the device, inputs off and outputs disabled, resets I²C HIGH: Normal operation
DIAG	L12	Input (with 48-kΩ pulldown) 2.5-V or 3.3-V CMOS	GPIO mode HIGH: Enables the same data on the line side (Port C) to be output on both fabric side ports (Port A and Port B). LOW: Normal operation See Table 2 and Figure 15	I²C mode No action needed
LN_0_EN LN_1_EN LN_2_EN LN_3_EN	K12 K13 L14 L13	Input (with 48-kΩ pullup) 2.5-V or 3.3-V CMOS	GPIO mode LN_x_EN = High, enables lane x of ports A, B, and C LN_x_EN = Low, disables lane x of ports A, B, and C	I²C mode No action needed
DIS_AGC_A DIS_AGC_B DIS_AGC_C	B1 C1 D1	Input (with 48-kΩ pulldown) 2.5-V or 3.3-V CMOS	GPIO mode Disables the AGC loop internal to the SN65LVCP114 DIS_AGC = High, disables the AGC loop DIS_AGC = Low, enables the AGC loop	I²C mode No action needed
VOD_A VOD_B VOD_C	N2 M2 L2	Input, 2.5-V or 3.3-V CMOS - 3-state	GPIO mode HIGH: selects VOD output range: 1.2 V maximum and a gain of 2.2 LOW: selects VOD output range: 600 mV maximum and a gain of 1.1 If the VOD_x signal is left floating, the signal defaults to 1.2 V maximum and a gain of 2.2	I²C mode No action needed
Gain_A Gain_B Gain_C	E2 D2 E3	Input, 2.5-V or 3.3-V CMOS - 3-state	GPIO mode HIGH: Receiver gain = 1 LOW: Receiver gain = 0.5 If the Gain_x signal is left floating, the signal defaults to 0.5	I²C mode No action needed
SDA	A2	Input / output, open-drain output	GPIO mode No action needed	I²C mode I²C data. Connect a 10-kΩ pullup resistor externally
SCL	B2	Input, open-drain input	GPIO mode No action needed	I²C mode I²C clock. Connect a 10-kΩ pullup resistor externally
FST_SW	D13	Input (with 48-kΩ pullup) 2.5-V or 3.3-V CMOS input	GPIO mode HIGH: Fast switching; the idle outputs are squelched (see tSM specification). LOW: Slow switching; the idle outputs are powered off (see tSM1 specification).	I²C mode No action needed
I2C_SEL	D14	Input (with 48-kΩ pulldown) 2.5-V or 3.3-V CMOS input	Configures the device in I²C or GPIO mode of operation HIGH: Enables I²C mode LOW: Enables GPIO mode
POWER SUPPLY
VCC	B4, B5, B7, B8, B10, B11, B13, E13, G2, G13, H2, H13, K2,N4, N5, N7, N10, N11, N13	Power, 2.5 V ±5% or 3.3 V ±5%	Power supply pins
GROUND
GND	A5, A8, A11, B3, B6, B9, B12, C4, C7, C10,D12, F2, F13,G1, G12, G1, G12, H3, H14,J2, J13, L3, M5,M8, M11, N3, N6, N8, N9, N12, P4, P7, P10	Ground	Ground pins
GND_CenterPad	E6, E7 , E8, E9, E10, F5, F6, F7, F8, F9, F10, G5, G6, G7,G8, G9, G10, H5, H6, H7, H8, H9, H10, J5, J6, J7, J8, J9, J10, K5, K6, K7,K8, K9, K10	Ground	These pins must be connected to the GND plane.