Add a decoupling capacitor from VCC to GND. The capacitor needs to be
placed physically close to the device and electrically close to both the
VCC and GND pins. An example layout is shown in the Layout
section.
Ensure the capacitive load at the
output is ≤ 50 pF. This is not a hard
limit, however it will ensure optimal performance. This can be accomplished by
providing short, appropriately sized traces from the SN74HCT165-Q1 to the receiving device(s).
Ensure the resistive load at the output is larger than (VCC /
IO(max)) Ω. This will ensure that the maximum output current from
the Absolute Maximum Ratings is not violated. Most CMOS inputs have a
resistive load measured in megaohms; much larger than the minimum calculated
above.
Thermal issues are rarely a
concern for logic gates, however the power consumption and thermal increase can
be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation.