SCES656E February 2006 – November 2016 SN74LV4046A
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The most common use for the digital phased-locked loop (PLL) device is to match the VCO output to the same phase as the incoming signal and produce an error signal (DEMOUT) that indicates the amount of phase shift required for the match. This can be used as part of many complex systems.
Table 1 and Table 2 lists the design requirements of the SN74LV4046A.
COMPONENT | VALUE |
---|---|
R1 | 3 kΩ to 50 kΩ |
R2 | 3 kΩ to 50 kΩ |
R1 || R2 | > 2.7 kΩ |
C1 | > 40 pF |
R3 | 1 kΩ |
C2 | 1 uF |
R5 | 50 kΩ to 300 kΩ |
CHIP SECTION | CPD | UNIT |
---|---|---|
Comparator 1 | 120 | pF |
VCO | 120 |
Table 3 lists the application curves in the Typical Characteristics section.