SLAS988B June   2014  – August 2015 TAS5756M

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1. 6.1 Internal Pin Configurations
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  MCLK Timing
    7. 7.7  Serial Audio Port Timing - Slave Mode
    8. 7.8  Serial Audio Port Timing - Master Mode
    9. 7.9  I2C Bus Timing - Standard
    10. 7.10 I2C Bus Timing - Fast
    11. 7.11 SPK_MUTE Timing
    12. 7.12 Power Dissipation
    13. 7.13 Typical Characteristics
      1. 7.13.1 Bridge Tied Load (BTL) Configuration Curves
      2. 7.13.2 Parallel Bridge Tied Load (PBTL) Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power-on-Reset (POR) Function
      2. 8.3.2 Device Clocking
      3. 8.3.3 Serial Audio Port
        1. 8.3.3.1 Clock Master Mode from Audio Rate Master Clock
        2. 8.3.3.2 Clock Master from a Non-Audio Rate Master Clock
        3. 8.3.3.3 Clock Slave Mode with 4-Wire Operation (SCLK, MCLK, LRCK/FS, SDIN)
        4. 8.3.3.4 Clock Slave Mode with SLCK PLL to Generate Internal Clocks (3-Wire PCM)
          1. 8.3.3.4.1 Clock Generation using the PLL
          2. 8.3.3.4.2 PLL Calculation
            1. 8.3.3.4.2.1 Examples:
        5. 8.3.3.5 Serial Audio Port - Data Formats and Bit Depths
          1. 8.3.3.5.1 Data Formats and Master/Slave Modes of Operation
        6. 8.3.3.6 Input Signal Sensing (Power-Save Mode)
        7. 8.3.3.7 Serial Data Output
      4. 8.3.4 Modulation Scheme
        1. 8.3.4.1 BD-Modulation
      5. 8.3.5 miniDSP Audio Processing Engine
        1. 8.3.5.1 HybridFlow Architecture
        2. 8.3.5.2 Volume Control
          1. 8.3.5.2.1 Digital Volume Control
            1. 8.3.5.2.1.1 Emergency Volume Ramp Down
      6. 8.3.6 Adjustable Amplifier Gain and Switching Frequency Selection
      7. 8.3.7 Error Handling and Protection Suite
        1. 8.3.7.1 Device Overtemperature Protection
        2. 8.3.7.2 SPK_OUTxx Overcurrent Protection
        3. 8.3.7.3 DC Offset Protection
        4. 8.3.7.4 Internal VAVDD Undervoltage-Error Protection
        5. 8.3.7.5 Internal VPVDD Undervoltage-Error Protection
        6. 8.3.7.6 Internal VPVDD Overvoltage-Error Protection
        7. 8.3.7.7 External Undervoltage-Error Protection
        8. 8.3.7.8 Internal Clock Error Notification (CLKE)
      8. 8.3.8 GPIO Port and Hardware Control Pins
      9. 8.3.9 I2C Communication Port
        1. 8.3.9.1 Slave Address
        2. 8.3.9.2 Register Address Auto-Increment Mode
        3. 8.3.9.3 Packet Protocol
        4. 8.3.9.4 Write Register
        5. 8.3.9.5 Read Register
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Audio Port Operating Modes
      2. 8.4.2 Communication Port Operating Modes
      3. 8.4.3 Audio Processing Modes via HybridFlow Audio Processing
      4. 8.4.4 Speaker Amplifier Operating Modes
        1. 8.4.4.1 Stereo Mode
        2. 8.4.4.2 Mono Mode
        3. 8.4.4.3 Bi-Amp Mode
        4. 8.4.4.4 Master and Slave Mode Clocking for Digital Serial Audio Port
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 External Component Selection Criteria
      2. 9.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing
      3. 9.1.3 Amplifier Output Filtering
      4. 9.1.4 Programming the TAS5756M
        1. 9.1.4.1 Resetting the TAS5756M registers and modules
        2. 9.1.4.2 Adaptive Mode and using CRAM buffers
    2. 9.2 Typical Applications
      1. 9.2.1 2.0 (Stereo BTL) System
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Step One: Hardware Integration
          2. 9.2.1.2.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.1.2.3 Step Three: Software Integration
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Mono (PBTL) Systems
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Step One: Hardware Integration
          2. 9.2.2.2.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.2.2.3 Step Three: Software Integration
        3. 9.2.2.3 Application Specific Performance Plots for Mono (PBTL) Systems
      3. 9.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems
        1. 9.2.3.1 Basic 2.1 System (TAS5756M Device + Simple Digital Input Amplifier)
        2. 9.2.3.2 Advanced 2.1 System (Two TAS5756M devices)
        3. 9.2.3.3 Design Requirements
        4. 9.2.3.4 Detailed Design Procedure
          1. 9.2.3.4.1 Step One: Hardware Integration
          2. 9.2.3.4.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.3.4.3 Step Three: Software Integration
        5. 9.2.3.5 Application Specific Performance Plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems
      4. 9.2.4 2.2 (Dual Stereo BTL) Systems
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
          1. 9.2.4.2.1 Step One: Hardware Integration
          2. 9.2.4.2.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.4.2.3 Step Three: Software Integration
        3. 9.2.4.3 Application Specific Performance Plots for 2.2 (Dual Stereo BTL) Systems
      5. 9.2.5 1.1 (Dual BTL, Bi-Amped) Systems
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Detailed Design Procedure
          1. 9.2.5.2.1 Step One: Hardware Integration
          2. 9.2.5.2.2 Step Two: HybridFlow Selection and System Level Tuning
          3. 9.2.5.2.3 Step Three: Software Integration
        3. 9.2.5.3 Application Specific Performance Plots for 1.1 (Dual BTL, Bi-Amped) Systems
  10. 10Power Supply Recommendations
    1. 10.1 Power Supplies
      1. 10.1.1 DVDD Supply
      2. 10.1.2 PVDD Supply
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General Guidelines for Audio Amplifiers
      2. 11.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 11.1.3 Optimizing Thermal Performance
        1. 11.1.3.1 Device, Copper, and Component Layout
        2. 11.1.3.2 Stencil Pattern
          1. 11.1.3.2.1 PCB footprint and Via Arrangement
            1. 11.1.3.2.1.1 Solder Stencil
    2. 11.2 Layout Example
      1. 11.2.1 2.0 (Stereo BTL) System
      2. 11.2.2 Mono (PBTL) System
      3. 11.2.3 2.1 (Stereo BTL + Mono PBTL) Systems
      4. 11.2.4 2.2 (Dual Stereo BTL) Systems
      5. 11.2.5 1.1 (Bi-Amped BTL) Systems
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
      2. 12.1.2 Development Support
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

One of the most significant benefits of the TAS5756M device is the ability to be used in a variety of applications and with an assortment of signal processing options. This section details the information required to configure the device for several popular configurations and provides guidance on integrating the TAS5756M device into the larger system.

9.1.1 External Component Selection Criteria

The Supporting Component Requirements table in each application description section lists the details of the supporting required components in each of the System Application Schematics.

Where possible, the supporting component requirements have been consolidated to minimize the number of unique components which are used in the design. Component list consolidation is a method to reduce the number of unique part numbers in a design, to ease inventory management, and reduce the manufacturing steps during board assembly. For this reason, some capacitors are specified at a higher voltage than what would normally be required. An example of this is a 50-V capacitor may be used for decoupling of a 3.3-V power supply net.

In this example, a higher voltage capacitor can be used even on the lower voltage net to consolidate all caps of that value into a single component type. Similarly, a several unique resistors, having all the same size and value but with different power ratings can be consolidated by using the highest rated power resistor for each instance of that resistor value.

While this consolidation may seem excessive, the benefits of having fewer components in the design may far outweigh the trivial cost of a higher voltage capacitor. If lower voltage capacitors are already available elsewhere in the design, they can be used instead of the higher voltage capacitors. In all situations, the voltage rating of the capacitors must be at least 1.45 times the voltage of the voltage which appears across them. The power rating of the capacitors should be 1.5 times to 1.75 times the power dissipated in it during normal use case.

9.1.2 Component Selection Impact on Board Layout, Component Placement, and Trace Routing

Because the layout is important to the overall performance of the circuit, the package size of the components shown in the component list were intentionally chosen to allow for proper board layout, component placement, and trace routing. In some cases, traces are passed in between two surface mount pads or ground plane extends from the TAS5756M device between two pads of a surface mount component and into to the surrounding copper for increased heat-sinking of the device. While components may be offered in smaller or larger package sizes, it is highly recommended that the package size remain identical to that used in the application circuit as shown. This consistency ensures that the layout and routing can be matched very closely, optimizing thermal, electromagnetic, and audio performance of the TAS5756M device in circuit in the final system.

9.1.3 Amplifier Output Filtering

The TAS5756M device is often used with a low-pass filter, which is used to filter out the carrier frequency of the PWM modulated output. This filter is frequently referred to as the L-C Filter, due to the presence of an inductive element L and a capacitive element C to make up the 2-pole filter.

The L-C filter removes the carrier frequency, reducing electromagnetic emissions and smoothing the current waveform which is drawn from the power supply. The presence and size of the L-C filter is determined by several system level constraints. In some low-power use cases that have no other circuits which are sensitive to EMI, a simple ferrite bead or ferrite bead and capacitor can replace the traditional large inductor and capacitor that are commonly used. In other high-power applications, large toroid inductors are required for maximum power and film capacitors may be preferred due to audio characteristics. Refer to the application report SLOA119 for a detailed description on proper component selection and design of an L-C filter based upon the desired load and response.

9.1.4 Programming the TAS5756M

The device includes an I2C compatible control port to configure the internal registers of the TAS5756M. The Control Console software provided by TI is required to configure the device for operation with the various HybridFlows. More details regarding programming steps, and a few important notes are available below and also in the design examples that follow.

9.1.4.1 Resetting the TAS5756M registers and modules

The TAS5756M device has several methods by which it can reset the register, interpolation filters, and DAC modules. The registers offer the flexibility to do these in or out of shutdown as well as in or out of standby. However, there can be issues if the reset bits are toggled in certain illegal operation modes.

Any of the following routines can be used with no issue:

  • Reset Routine 1
    • Place device in Standby
    • Reset modules
  • Reset Routine 2
    • Place device in Standby + Power Down
    • Reset registers
  • Reset Routine 3
    • Place device in Power Down
    • Reset registers
  • Reset Routine 4
    • Place device in Standby
    • Reset registers
  • Reset Routine 5
    • Place device in Standby + Power Down
    • Reset modules + Reset registers
  • Reset Routine 6
    • Place device in Power Down
    • Reset modules + Reset registers
  • Reset Routine 7
    • Place device in Standby
    • Reset modules + Reset registers

There are two reset routines which are not support and should be avoided. If used, they can cause the device to become unresponsive. These unsupported routines are shown below.

  • Unsupported Reset Routine 1 (do not use)
    • Place device in Standby + Power Down
    • Reset modules
  • Unsupported Reset Routine 2 (do not use)
    • Place device in Power Down
    • Reset modules

9.1.4.2 Adaptive Mode and using CRAM buffers

The TAS5756M device has the ability to operate in a mode called "adaptive mode". In this mode, coefficients used the configuration of DSP blocks can be switched "on-the-fly", which means changed while the DSP is running and not muted or placed into shutdown. When adaptive buffering is enabled the configuration file generated by the Control Console software will initialize the coefficients in buffer A and the coefficients in buffer B with identical values. For example, if there is a mixing component in the HybridFlow which has been enabled to change while the DSP is running, the coefficient corresponding to the mixer coefficient is presented in both coefficient buffer A and B when the user clicks on the "run" button in the GUI. If the coefficient is to be changed "on-the-fly", there is a bit called "Switch Active CRAM" at location P44-R1-B0 that instructs the miniDSP to swap buffers A and B when this bit is set. When the user needs to change the value of the coefficient stored in the CRAM buffer, the host processor should do the following:

  1. Write the new value of the coefficient to buffer A
  2. Set the buffer-swap bit (P44-R1-B0).
  3. Check the state of the Active CRAM Selection bit (P44-R1-B2) to ensure that the proper CRAM buffer is being used.
  4. Write the new value of the unused buffer to make sure that both buffers remain in sync.
  5. Repeat, if necessary, for each subsequent changing of this coefficient, switching between buffer A and buffer B.

At the end of each frame, the miniDSP sees if this bit is set. If it is, it swaps the buffer from A to B or vice versa. At the same time, it clears the bit that was set by host.

9.2 Typical Applications

9.2.1 2.0 (Stereo BTL) System

For the stereo (BTL) PCB layout, see Figure 86.

A 2.0 system generally refers to a system in which there are two full range speakers without a separate amplifier path for the speakers which reproduce the low-frequency content. In this system, two channels are presented to the amplifier via the digital input signal. These two channels are amplified and then sent to two separate speakers. In some cases, the amplified signal is further separated based upon frequency by a passive crossover network after the L-C filter. Even so, the application is considered 2.0.

Most commonly, the two channels are a pair of signals called a stereo pair, with one channel containing the audio for the left channel and the other channel containing the audio for the right channel. While certainly the two channels can contain any two audio channels, such as two surround channels of a multi-channel speaker system, the most popular occurrence in two channels systems is a stereo pair.

It is important to note that the HybridFlows which have been developed for specifically for stereo applications will frequently apply the same equalizer curves to the left channel and the right channel. This maximizes the processing capabilities of each HybridFlow by minimizing the cycles required by the BiQuad filters.

When two signals that are not two separate signals, but instead are derived from a single signal which is separated into low frequency and high frequency by the signal processor, the application is commonly referred to as 1.1 or Bi-Amped systems.Figure 79 shows the 2.0 (Stereo BTL) system application.

TAS5756M typ_app_stereo_btl_20_slas988.gifFigure 79. 2.0 (Stereo BTL) System Application Schematic

9.2.1.1 Design Requirements

  • Power supplies:
    • 3.3-V supply
    • 5-V to 24-V supply
  • Communication: host processor serving as I2C compliant master
  • External memory (such as EEPROM and flash) used for coefficients and RAM portions of HybridFlow < 5 kB

The requirements for the supporting components for the TAS5756M device in a Stereo 2.0 (BTL) system is provided in Table 22.

Table 22. Supporting Component Requirements for Stereo 2.0 (BTL) Systems

REFERENCE
DESIGNATOR		 VALUE SIZE DETAILED DESCRIPTION
U100 TAS5756M 48 Pin TSSOP Digital-input, closed-loop class-D amplifier with HybridFlow processing
R100 See Adjustable Amplifier Gain and Switching Frequency Selection section 0402 1%, 0.063 W
R101 0402 1%, 0.063 W
L100, L101, L102, L103 See Amplifier Output Filtering section
C100, C121 0.1 µF 0402 Ceramic, 0.1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C104, C108, C111, C115 0.22 µF 0603 Ceramic, 0.22 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C109, C110, C116, C117 0.68 µF 0805 Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
C103 1 µF 0603
(this body size chosen to aid in trace routing)		 Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 16 V
C105, C118, C119, C120 1 µF 0402 Ceramic, 1 µF, 6.3V, ±10%, X5R
C106, C107, C113, C114 2.2 µF 0402 Ceramic, 2.2 µF, ±10%, X5R
At a minimum, voltage rating must be > 10V, however higher voltage caps have been shown to have better stability under DC bias please follow the guidance provided in the TAS5756MDCAEVM for suggested values.
C101, C102, C122, C123 22 µF 0805 Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Step One: Hardware Integration

  • Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
  • Following the recommended component placement, board layout and routing give in the example layout above, integrate the device and its supporting components into the system PCB file.
    • The most critical section of the circuit is the power supply inputs, the amplifier output signals, and the high-frequency signals which go to the serial audio port. Constructing these signals to ensure they are given precedent as design trade-offs are made is recommended.
    • For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is necessary, go to the E2E forum to request a layout review.

9.2.1.2.2 Step Two: HybridFlow Selection and System Level Tuning

  • Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to select the HybridFlow that meets the needs of the target application.
  • Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577.

9.2.1.2.3 Step Three: Software Integration

  • Use the Register Dump feature of the PPC software to generate a baseline configuration file.
  • Generate additional configuration files based upon operating modes of the end-equipment and integrate static configuration information into initialization files.
  • Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the main system program.

9.2.1.3 Application Curves

Table 23 shows the application specific performance plots for Stereo 2.0 (BTL) systems.

Table 23. Relevant Performance Plots

PLOT TITLE FIGURE NUMBER
Output Power vs PVDD Figure 23
THD+N vs Frequency, VPVDD = 12 V Figure 24
THD+N vs Frequency, VPVDD = 15 V Figure 25
THD+N vs Frequency, VPVDD = 18 V Figure 26
THD+N vs Frequency, VPVDD = 24 V Figure 27
THD+N vs Power, VPVDD = 12 V Figure 28
THD+N vs Power, VPVDD = 15 V Figure 29
THD+N vs Power, VPVDD = 18 V Figure 30
THD+N vs Power, VPVDD = 24 V Figure 31
Idle Channel Noise vs PVDD Figure 32
Efficiency vs Output Power Figure 33
Idle Current Draw (Filterless) vs PVDD Figure 34
Idle Current Draw (Traditional LC Filter) vs PVDD Figure 35
DVDD PSRR vs. Frequency Figure 38
AVDD PSRR vs. Frequency Figure 39
CPVDD PSRR vs. Frequency Figure 40
Powerdown Current Draw vs. PVDD Figure 41

9.2.2 Mono (PBTL) Systems

For the mono (PBTL) PCB layout, see Figure 88.

A mono system refers to a system in which the amplifier is used to drive a single loudspeaker. Parallel Bridge Tied Load (PBTL) indicates that the two full-bridge channels of the device are placed in parallel and drive the loudspeaker simultaneously using an identical audio signal. The primary benefit of operating the TAS5756M device in PBTL operation is to reduce the power dissipation and increase the current sourcing capabilities of the amplifier output. In this mode of operation, the current limit of the audio amplifier is approximately doubled while the on-resistance is approximately halved.

The loudspeaker can be a full-range transducer or one that only reproduces the low-frequency content of an audio signal, as in the case of a powered subwoofer. Often in this use case, two stereo signals are mixed together and sent through a low-pass filter to create a single audio signal which contains the low frequency information of the two channels. Conversely, advanced digital signal processing can create a low-frequency signal for a multichannel system, with audio processing which is specifically targeted on low-frequency effects.

Although any of the HybridFlows can be made to work with a mono speaker, it is strongly recommended that HybridFlows which have been created specifically for mono applications be used. These HybridFlows contain the mixing and filtering required to generate the mono signal. They also include processing which is targeted at improving the low-frequency performance of an audio system- a feature that, while targeted at subwoofers, can also be used to enhance the low-frequency performance of a full-range speaker.

Because low-frequency signals are not perceived as having a direction (at least to the extent of high-frequency signals) it is common to reproduce the low-frequency content of a stereo signal that is sent to two separate channels. This configuration pairs one device in Mono PBTL configuration and another device in Stereo BTL configuration in a single system called a 2.1 system. The Mono PBTL configuration is detailed in the 2.1 (Stereo BTL + External Mono Amplifier) Systems section.

TAS5756M typ_app_mono_pbtl_slas988.gifFigure 80. Mono (PBTL) System Application Schematic

9.2.2.1 Design Requirements

  • Power supplies:
    • 3.3-V supply
    • 5-V to 24-V supply
  • Communication: Host processor serving as I2C compliant master
  • External memory (EEPROM, flash, and others) used for coefficients and RAM portions of HybridFlow < 5 kB

The requirements for the supporting components for the TAS5756M device in a Mono (PBTL) system is provided in Table 24.

Table 24. Supporting Component Requirements for Mono (PBTL) Systems

REFERENCE
DESIGNATOR		 VALUE SIZE DETAILED DESCRIPTION
U200 TAS5756M 48 Pin TSSOP Digital-input, closed-loop class-D amplifier with HybridFlow processing
R200 See Adjustable Amplifier Gain and Switching Frequency Selection section 0402 1%, 0.063 W
R201 0402 1%, 0.063 W
R202 0402 1%, 0.063 W
L200, L201 See Amplifier Output Filtering section
C216, C201 0.1 µF 0402 Ceramic, 0.1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C208, C209, C214, C215 0.22 µF 0603 Ceramic, 0.22 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C220, C221 0.68 µF 0805 Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
C200 1 µF 0603
(this body size chosen to aid in trace routing)		 Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 16 V
C205, C211, C213, C212 1 µF 0402 Ceramic, 1 µF, 6.3 V, ±10%, X5R
C202, C217, C352, C367 1 µF 0805
(this body size chosen to aid in trace routing)		 Ceramic, 1 µF, ±10%, X5R
Voltage rating must be > 1.45 × VPVDD
C206, C207 2.2 µF 0402 Ceramic, 2.2 µF, ±10%, X5R
At a minimum, voltage rating must be > 10V, however higher voltage caps have been shown to have better stability under DC bias please follow the guidance provided in the TAS5756MDCAEVM for suggested values.
C203, C218 22 µF 0805 Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD
C204, C219 390 µF 10 × 10 Aluminum, 390 µF, ±20%, 0.08-Ω
Voltage rating must be > 1.45 × VPVDD Anticipating that this application circuit would be followed for higher power subwoofer applications, these capacitors are added to provide local current sources for low-frequency content. These capacitors can be reduced or even removed based upon final system testing, including critical listening tests when evaluating low-frequency designs.

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Step One: Hardware Integration

  • Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
  • Following the recommended component placement, board layout and routing give in the example layout above, integrate the device and its supporting components into the system PCB file.
    • The most critical section of the circuit is the power supply inputs, the amplifier output signals, and the high-frequency signals which go to the serial audio port. Constructing these signals to ensure they are given precedent as design trade-offs are made is recommended.
    • For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is necessary, go to the E2E forum to request a layout review.

9.2.2.2.2 Step Two: HybridFlow Selection and System Level Tuning

  • Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to select the HybridFlow that meets the needs of the target application.
  • Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577.

9.2.2.2.3 Step Three: Software Integration

  • Use the Register Dump feature of the PPC software to generate a baseline configuration file.
  • Generate additional configuration files based upon operating modes of the end-equipment and integrate static configuration information into initialization files.
  • Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the main system program.

9.2.2.3 Application Specific Performance Plots for Mono (PBTL) Systems

Table 25. Relevant Performance Plots

PLOT TITLE FIGURE NUMBER
Output Power vs PVDD Figure 42
THD+N vs Frequency, VPVDD = 12 V Figure 43
THD+N vs Frequency, VPVDD = 15 V Figure 44
THD+N vs Frequency, VPVDD = 18 V Figure 45
THD+N vs Frequency, VPVDD = 24 V Figure 46
THD+N vs Power, VPVDD = 12 V Figure 47
THD+N vs Power, VPVDD = 15 V Figure 48
THD+N vs Power, VPVDD = 18 V Figure 49
THD+N vs Power, VPVDD = 24 V Figure 50
Idle Channel Noise vs PVDD Figure 51
Efficiency vs Output Power Figure 52
Idle Current Draw (filterless) vs PVDD Figure 57
Idle Current Draw (traditional LC filter) vs PVDD Figure 58
PVDD PSRR vs Frequency Figure 53
DVDD PSRR vs. Frequency Figure 54
AVDD PSRR vs. Frequency Figure 55
CPVDD PSRR vs. Frequency Figure 56
Powerdown Current Draw vs. PVDD Figure 59

9.2.3 2.1 (Stereo BTL + External Mono Amplifier) Systems

Figure 90 shows the PCB Layout for the 2.1 System.

To increase the low-frequency output capabilities of an audio system, a single subwoofer can be added to the system. Because the spatial clues for audio are predominately higher frequency than that reproduced by the subwoofer, often a single subwoofer can be used to reproduce the low frequency content of several other channels in the system. This is frequently referred to as a dot one system. A stereo system with a subwoofer is referred to as a 2.1 (two-dot-one), a 3 channel system with subwoofer is referred to as a 3.1 (three-dot-one), a popular surround system with five speakers and one subwoofer is referred to as a 5.1, and so on.

9.2.3.1 Basic 2.1 System (TAS5756M Device + Simple Digital Input Amplifier)

In the most basic 2.1 system, a subwoofer is added to a stereo left and right pair of speakers as discussed above. The audio amplifiers include one TAS5756M device for the high frequency channels and one simple digital input device without integrated audio processing for the subwoofer channel. A member of the popular TAS5760xx family of devices is a popular choice for the subwoofer amplifier. In this system, the subwoofer content is generated by summing the two channels of audio and sending them through a high-pass filter to filter out the high frequency content. This is then sent to the SDIN pin of the subwoofer amplifier, which is operating in PBTL, via the SDOUT line of the TAS5756M device . In the basic 2.1 system, only HybridFlows which included subwoofer signal generation can be used, because the subwoofer amplifier depends on the TAS5756M device to create its stereo low-frequency input signal.

9.2.3.2 Advanced 2.1 System (Two TAS5756M devices)

In higher performance systems, the subwoofer output can be enhanced using digital audio processing as was done in the high-frequency channels. To accomplish this, two TAS5756M devices are used- one for the high frequency left and right speakers and one for the mono subwoofer speaker. In this system, the audio signal can be sent from the TAS5756M device through the SDOUT pin. Alternatively, the subwoofer amplifier can accept the same digital input as the stereo, which might come from a central systems processor. In advanced 2.1 systems, any HybridFlow can be used for the subwoofer, provided the sample rates for the two are the same. While any of the HybridFlows can be used, it is highly recommended that only mono HybridFlows are used for the subwoofer. Doing so streamlines development time and effort by minimizing confusion and complexity.

TAS5756M typ_app_21_stereo_btl_mono_pbtl_slas988.gifFigure 81. 2.1 (Stereo BTL + External Mono Amplifier) Application Schematic

9.2.3.3 Design Requirements

  • Power supplies:
    • 3.3-V supply
    • 5-V to 24-V supply
  • Communication: Host processor serving as I2C compliant master
  • External memory (EEPROM, flash, and others) used for coefficients and RAM portions of HybridFlow < 5 kB

The requirements for the supporting components for the TAS5756M device in a 2.1 (Stereo BTL + External Mono Amplifier) system is provided in Table 26.

Table 26. Supporting Component Requirements for 2.1 (Stereo BTL + External Mono Amplifier) Systems

REFERENCE
DESIGNATOR		 VALUE SIZE DETAILED DESCRIPTION
U300 TAS5756M 48 Pin TSSOP Digital-input, closed-loop class-D amplifier with HybridFlow processing
R300, R350 SeeAdjustable Amplifier Gain and Switching Frequency Selection section 0402 1%, 0.063 W
R301, R351 0402 1%, 0.063 W
R352 0402 1%, 0.063 W
L300, L301, L302, L303 See Amplifier Output Filtering section
L350, L351
C394, C395, C396, C397, C398, C399 0.01 µF 0603 Ceramic, 0.01 µF, 50 V, +/-10%, X7R
C300, C321, C351, C366 0.1 µF 0402 Ceramic, 0.1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C304, C308, C311, C315, C358, C359, C364, C365 0.22 µF 0603 Ceramic, 0.22 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C309, C310, C316, C317, C370, C371 0.68 µF 0805 Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
C303, C350, C312, C360 1 µF 0603 Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C305, C318, C319, C320, C355, C361, C363, C312, C362 1 µF 0402 Ceramic, 1 µF, 6.3V, ±10%, X5R
C352, C367 1 µF 0805 Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C306, C307, C313, C314, C356, C357, 2.2 µF 0402 Ceramic, 2.2 µF, ±10%, X5R
Voltage rating must be > 1.45 × VPVDD
C301, C302, C322, C323, C353, C368 22 µF 0805 Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD
C354, C369 390 µF 10 × 10 Aluminum, 390 µF, ±20%, 0.08 Ω
Voltage rating must be > 1.45 × VPVDD

9.2.3.4 Detailed Design Procedure

9.2.3.4.1 Step One: Hardware Integration

  • Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
  • Following the recommended component placement, board layout and routing give in the example layout above, integrate the device and its supporting components into the system PCB file.
    • The most critical section of the circuit is the power supply inputs, the amplifier output signals, and the high-frequency signals which go to the serial audio port. Constructing these signals to ensure they are given precedent as design trade-offs are made is recommended.
    • For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is necessary, go to the E2E forum to request a layout review.

9.2.3.4.2 Step Two: HybridFlow Selection and System Level Tuning

  • Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to select the HybridFlow that meets the needs of the target application.
  • Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577.

9.2.3.4.3 Step Three: Software Integration

  • Use the Register Dump feature of the PPC software to generate a baseline configuration file.
  • Generate additional configuration files based upon operating modes of the end-equipment and integrate static configuration information into initialization files.
  • Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the main system program.

9.2.3.5 Application Specific Performance Plots for 2.1 (Stereo BTL + External Mono Amplifier) Systems

Table 27. Relevant Performance Plots

DEVICE PLOT TITLE FIGURE NUMBER
U300 Output Power vs PVDD Figure 23
THD+N vs Frequency, VPVDD = 12 V Figure 24
THD+N vs Frequency, VPVDD = 15 V Figure 25
THD+N vs Frequency, VPVDD = 18 V Figure 26
THD+N vs Frequency, VPVDD = 24 V Figure 27
THD+N vs Power, VPVDD = 12 V Figure 28
THD+N vs Power, VPVDD = 15 V Figure 29
THD+N vs Power, VPVDD = 18 V Figure 30
THD+N vs Power, VPVDD = 24 V Figure 31
Idle Channel Noise vs PVDD Figure 32
Efficiency vs Output Power Figure 33
Idle Current Draw (Filterless) vs PVDD Figure 34
Idle Current Draw (Traditional LC Filter) vs PVDD Figure 58
U301 Output Power vs PVDD Figure 42
THD+N vs Frequency, VPVDD = 12 V Figure 43
THD+N vs Frequency, VPVDD = 15 V Figure 44
THD+N vs Frequency, VPVDD = 18 V Figure 45
THD+N vs Frequency, VPVDD = 24 V Figure 46
THD+N vs Power, VPVDD = 12 V Figure 47
THD+N vs Power, VPVDD = 15 V Figure 48
THD+N vs Power, VPVDD = 18 V Figure 49
THD+N vs Power, VPVDD = 24 V Figure 50
Idle Channel Noise vs PVDD Figure 51
Efficiency vs Output Power Figure 52
Idle Current Draw (filterless) vs PVDD Figure 57
Idle Current Draw (traditional LC filter) vs PVDD Figure 58
PVDD PSRR vs Frequency Figure 53
U300
and
U301		 DVDD PSRR vs. Frequency Figure 38
AVDD PSRR vs. Frequency Figure 39
CPVDD PSRR vs. Frequency Figure 40
Powerdown Current Draw vs. PVDD Figure 41

9.2.4 2.2 (Dual Stereo BTL) Systems

For the 2.2 (Dual Stereo BTL) PCB layout, see Figure 92.

A 2.2 system consists of a stereo pair of loudspeakers with a pair of low frequency loudspeakers. In some cases, this is implemented as two stereo full-range speakers and two subwoofers. In others, it is implemented as two high frequency speakers and two mid-range speakers.

As in the case of the 2.1 system, the 2.2 system can be created by using the audio processing inside of the TAS5756M device and creating a subwoofer signal which is sent to a simple digital input amplifier like one of the TAS5760xx devices (or similar). This requires that a HybridFlow that contains a subwoofer generation processing block be used in the TAS5756M device. This signal is created by summing the left and right channel, filtering with a high-pass filter and sending it to the subwoofer amplifier. For this type of system, the TAS5756M device used for the high-frequency drivers must have a subwoofer generation processing block to provide the appropriate signal to the subwoofer amplifiers.

Alternatively, the low-frequency drivers can be driven by using two TAS5756M devices; each receiving their input from a central systems processor. This type of implementation allows for any stereo HybridFlow to be used for both the low-frequency and high-frequency drivers, increasing the processing options available for the system. This expands the processing capabilities of the system, introducing digital signal processing to the low-frequency drivers as well as the high-frequency drivers. This type of 2.2 system is described in Figure 82.

TAS5756M typ_app_stereo_btlx2_22_slas988.gifFigure 82. 2.2 (Dual Stereo BTL) Application Schematic

9.2.4.1 Design Requirements

  • Power Supplies:
    • 3.3-V Supply
    • 5-V to 24-V Supply
  • Communication: Host Processor serving as I2C Compliant Master
  • External Memory (EEPROM, Flash, Etc.) used for Coefficients and RAM portions of HybridFlow < 5 kB

The requirements for the supporting components for the TAS5756M device in a 2.2 (Dual Stereo BTL) System is provided in Figure 92.

Table 28. Supporting Component Requirements for 2.2 (Dual Stereo BTL) Systems

REFERENCE
DESIGNATOR		 VALUE SIZE DETAILED DESCRIPTION
U400, U401 TAS5756M device 48-pin TSSOP Digital Input, Closed-Loop Class-D Amplifier with HybridFlow Processing
R400, R450 See Figure 83 0402 1%, 0.063 W
R401, R451 See Figure 83 0402 1%, 0.063 W
L400, L401, L402, L403, L450, L451, L452, L453 See the Amplifier Output Filtering section
C492, C493, C494, C495, C496, C497, C498, C499 0.01 µF 0603 Ceramic, 0.01 µF, 50 V, ±10%, X7R
C400, C421, C450, C471 0.1 µF 0402 Ceramic, 0.1 µF, ±10%, X7R, Voltage rating must be > 1.45 × VPVDD
C404, C408, C411, C415, C454, C458, C461, C465 0.22 µF 0603 Ceramic, 0.22 µF, ±10%, X7R, Voltage rating must be > 1.45 × VPVDD
C409, C410, C416, C417, C459, C460, C466, C467 0.68 µF 0805 Ceramic, 0.68 µF, ±10%, X7R, Voltage rating must be > 1.8 × VPVDD
C403, C453, C462 1 µF 0603 Ceramic, 1 µF, ±10%, X7R, Voltage rating must be > 1.45 × VPVDD
C405, C418, C419, C420, C455, C468, C469, C470, C412, C462 1 µF 0402 Ceramic, 1 µF, 6.3V, ±10%, X5R
C406, C407, C413, C414, C456, C457, C463, C464 2.2 µF 0402 Ceramic, 2.2 µF, ±10%, X5R, Voltage rating must be > 1.45 × VPVDD
C401, C402, C422, C423, C451, C452, C472, C473 22 µF 0805 Ceramic, 22 µF, ±20%, X5R, Voltage rating must be > 1.45 × VPVDD

9.2.4.2 Detailed Design Procedure

9.2.4.2.1 Step One: Hardware Integration

  • Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
  • Following the recommended component placement, board layout and routing give in the example layout above, integrate the device and its supporting components into the system PCB file.
    • The most critical section of the circuit is the power supply inputs, the amplifier output signals, and the high-frequency signals which go to the serial audio port. Constructing these signals to ensure they are given precedent as design trade-offs are made is recommended.
    • For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is necessary, go to the E2E forum to request a layout review.

9.2.4.2.2 Step Two: HybridFlow Selection and System Level Tuning

  • Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to select the HybridFlow that meets the needs of the target application.
  • Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577.

9.2.4.2.3 Step Three: Software Integration

  • Use the Register Dump feature of the PPC software to generate a baseline configuration file.
  • Generate additional configuration files based upon operating modes of the end-equipment and integrate static configuration information into initialization files.
  • Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the main system program.

9.2.4.3 Application Specific Performance Plots for 2.2 (Dual Stereo BTL) Systems

Table 29. Relevant Performance Plots

PLOT TITLE PLOT NUMBER
Figure 23. Output Power vs PVDD C036
Figure 24. THD+N vs Frequency, VPVDD = 12 V C034
Figure 25. THD+N vs Frequency, VPVDD = 15 V C002
Figure 26. THD+N vs Frequency, VPVDD = 18 V C037
Figure 27. THD+N vs Frequency, VPVDD = 24 V C003
Figure 28. THD+N vs Power, VPVDD = 12 V C035
Figure 29. THD+N vs Power, VPVDD = 15 V C004
Figure 30. THD+N vs Power, VPVDD = 18 V C038
Figure 31. THD+N vs Power, VPVDD = 24 V C005
Figure 32. Idle Channel Noise vs PVDD C006
Figure 33. Efficiency vs Output Power C007
Figure 34. Idle Current Draw (Filterless) vs PVDD C013
Figure 35. Idle Current Draw (Traditional LC Filter) vs PVDD C015
Figure 38. DVDD PSRR vs. Frequency C028
Figure 39. AVDD PSRR vs. Frequency C029
Figure 40. CPVDD PSRR vs. Frequency C030
Figure 41. Powerdown Current Draw vs. PVDD C032

9.2.5 1.1 (Dual BTL, Bi-Amped) Systems

The 1.1 use case is a special application of the 2.0 stereo BTL system. In this system, two channels of an amplifier are used to reproduce a single channel of an audio signal that has been separated based on frequency. This configuration removes the need for passive cross-over elements inside of a loudspeaker, because the signal is separated into a low-frequency and a high-frequency component before it is amplified. Systems which operate in this configuration, in which separate amplifier channels drive the low and high-frequency loudspeakers directly, are often called “bi-amped” systems.

Popular applications for this configuration include:

  • Powered near-field monitors
  • Blue-tooth Speakers
  • Co-axial Loudspeakers
  • Surround/Fill Speakers for multi-channel audio

From a hardware perspective, the TAS5756M device is configured in the same way as the Stereo BTL system. However, special HybridFlows which support 1.1 operation must be used, because HybridFlows that are designed for stereo applications frequently apply the same equalizer curves to the left and the right hand channel. Additionally, many 1.1 HybridFlows include a delay element which can improve time alignment between two loudspeakers that are mounted on the same baffle some distance apart.

For the 1.1 (Dual BTL, Bi-Amped) PCB layout, see Figure 94.

TAS5756M typ_app_11_bi-amped_btl_slas988.gifFigure 83. 1.1 (Dual BTL, Bi-Amped) Application Schematic

9.2.5.1 Design Requirements

  • Power Supplies:
  • Communication: Host Processor serving as I2C Compliant Master
  • External Memory (EEPROM, Flash, Etc.) used for Coefficients and RAM portions of HybridFlow < 5 kB

The requirements for the supporting components for the TAS5756M device in a Dual BTL, Bi-Amped System is provided in Figure 94.

Table 30. Supporting Component Requirements for 1.1 (Dual BTL, Bi-Amped) Systems

REFERENCE
DESIGNATOR		 VALUE SIZE DETAILED DESCRIPTION
U500 TAS5756M 48 Pin TSSOP Digital-input, closed-loop class-D amplifier with HybridFlow processing
R500 See Adjustable Amplifier Gain and Switching Frequency Selection section 0402 1%, 0.063 W
R501 0402 1%, 0.063 W
L500, L501, L502, L503 See Amplifier Output Filtering section
C596, C597, C598, C599 0.01 µF 0603 Ceramic, 0.01 µF, 50 V, ±10%, X7R
C500, C521 0.1 µF 0402 Ceramic, 0.1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C504, C508, C511, C515 0.22 µF 0603 Ceramic, 0.22 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C509, C510, C516, C517 0.68 µF 0805 Ceramic, 0.68 µF, ±10%, X7R
Voltage rating must be > 1.8 × VPVDD
C503 1 µF 0603 Ceramic, 1 µF, ±10%, X7R
Voltage rating must be > 1.45 × VPVDD
C505, C518, C519, C520, C512 1 µF 0402 Ceramic, 1 µF, 6.3V, ±10%, X5R
C506, C507, C513, C514 2.2 µF 0402 Ceramic, 2.2 µF, ±10%, X5R
Voltage rating must be > 1.45 × VPVDD
C501, C502, C522, C523 22 µF 805 Ceramic, 22 µF, ±20%, X5R
Voltage rating must be > 1.45 × VPVDD

9.2.5.2 Detailed Design Procedure

9.2.5.2.1 Step One: Hardware Integration

  • Using the Typical Application Schematic as a guide, integrate the hardware into the system schematic.
  • Following the recommended component placement, board layout and routing give in the example layout above, integrate the device and its supporting components into the system PCB file.
    • The most critical section of the circuit is the power supply inputs, the amplifier output signals, and the high-frequency signals which go to the serial audio port. Constructing these signals to ensure they are given precedent as design trade-offs are made is recommended.
    • For questions and support go to the E2E forums (e2e.ti.com). If deviating from the recommended layout is necessary, go to the E2E forum to request a layout review.

9.2.5.2.2 Step Two: HybridFlow Selection and System Level Tuning

  • Use the TAS5754/6M HybridFlow Processsor User Guide and HybridFlow Documentation (SLAU577) to select the HybridFlow that meets the needs of the target application.
  • Use the TAS5754_56MEVM evaluation module and the PurePath ControlConsole (PPC) software, to load the appropriate HybridFlow. Tune the end equipment by following the instructions in the SLAU577.

9.2.5.2.3 Step Three: Software Integration

  • Use the Register Dump feature of the PPC software to generate a baseline configuration file.
  • Generate additional configuration files based upon operating modes of the end-equipment and integrate static configuration information into initialization files.
  • Integrate dynamic controls (such as volume controls, mute commands, and mode-based EQ curves) into the main system program.

9.2.5.3 Application Specific Performance Plots for 1.1 (Dual BTL, Bi-Amped) Systems

Table 31. Relevant Performance Plots

PLOT TITLE PLOT NUMBER
Figure 23. Output Power vs PVDD C036
Figure 24. THD+N vs Frequency, VPVDD = 12 V C034
Figure 25. THD+N vs Frequency, VPVDD = 15 V C002
Figure 26. THD+N vs Frequency, VPVDD = 18 V C037
Figure 27. THD+N vs Frequency, VPVDD = 24 V C003
Figure 28. THD+N vs Power, VPVDD = 12 V C035
Figure 29. THD+N vs Power, VPVDD = 15 V C004
Figure 30. THD+N vs Power, VPVDD = 18 V C038
Figure 31. THD+N vs Power, VPVDD = 24 V C005
Figure 32. Idle Channel Noise vs PVDD C006
Figure 33. Efficiency vs Output Power C007
Figure 34. Idle Current Draw (Filterless) vs PVDD C013
Figure 35. Idle Current Draw (Traditional LC Filter) vs PVDD C015
Figure 38. DVDD PSRR vs. Frequency C028
Figure 39. AVDD PSRR vs. Frequency C029
Figure 40. CPVDD PSRR vs. Frequency C030
Figure 41. Powerdown Current Draw vs. PVDD C032
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