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7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Low-voltage digital, analog, charge pump supply	DVDD, AVDD, CPVDD	–0.3	3.9	V
PVDD supply	PVDD	–0.3	30	V
Input voltage for SPK_GAIN/FREQ and SPK_FAULT pins	V_I(AmpCtrl)	–0.3	V_GVDD+ 0.3	V
DVDD referenced digital inputs⁽²⁾	V_I(DigIn)	–0.5	V_DVDD + 0.5	V
Analog input into speaker amplifier	V_{I(SPK_INxx)}	–0.3	6.3	V
Voltage at speaker output pins	V_{I(SPK_OUTxx)}	–0.3	32	V
Ambient operating temperature, T_A		–25	85	°C
Storage temperature, T_stg		–40	125	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO1, GPIO2, LRCK/FS, MCLK, SCL, SCLK, SDA, SDIN, and SPK_MUTE.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
V_(POWER)	Power supply inputs	DVDD, AVDD, CPVDD	2.9		3.63	V
V_(POWER)	Power supply inputs	PVDD	4.5		26.4	V
R_SPK	Minimum speaker load	BTL Mode	3			Ω
R_SPK	Minimum speaker load	PBTL Mode	2			Ω
V_IH(DigIn)	Input logic high for DVDD referenced digital inputs⁽²⁾⁽¹⁾		0.9 × V_DVDD		V_DVDD	V
V_IL(DigIn)	Input logic low for DVDD referenced digital inputs⁽²⁾⁽²⁾		V_DVDD	0	0.1 × V_DVDD	V
L_OUT	Minimum inductor value in LC filter under short-circuit condition		1	4.7		µH

(1) The best practice for driving the input pins of the TAS5756M device is to power the drive circuit or pullup resistor from the same supply which provides the DVDD power supply.

(2) The best practice for driving the input pins of the TAS5756M device low is to pull them down, either actively or through pulldown resistors to the system ground.

7.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾		TAS5756M DCA (HTSSOP) 48 PINS			UNIT
THERMAL METRIC⁽¹⁾⁽²⁾		JEDEC STANDARD 2-LAYER PCB	JEDEC STANDARD 4-LAYER PCB	TAS5756MDCAEVM 4-LAYER PCB	UNIT
R_θJA	Junction-to-ambient thermal resistance	41.8	27.6	19.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	14.4	14.4	14.4	°C/W
R_θJB	Junction-to-board thermal resistance	9.4	9.4	9.4	°C/W
ψ_JT	Junction-to-top characterization parameter	0.6	0.6	2	°C/W
ψ_JB	Junction-to-board characterization parameter	8.1	9.3	4.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1	1	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(2) For the PCB layout, see the Using the TAS5754/6M HybridFlow Processor user's guide, SLAU577.

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL I/O
\|IIH\|1	Input logic high current level for DVDD referenced digital input pins⁽²⁾	V_IN(DigIn) = V_DVDD			10	µA
\|IIL\|1	Input logic low current level for DVDD referenced digital input pins⁽²⁾	V_IN(DigIn)= 0 V			–10	µA
V_IH1	Input logic high threshold for DVDD referenced digital inputs⁽²⁾		70%			V_DVDD
V_IL1	Input logic low threshold for DVDD referenced digital inputs⁽²⁾				30%	V_DVDD
V_OH(DigOut)	Output logic high voltage level⁽²⁾	I_OH = 4 mA	80%			V_DVDD
V_OL(DigOut)	Output logic low voltage level⁽²⁾	I_OH = –4 mA			22%	V_DVDD
V_{OL(SPK_FAULT)}	Output logic low voltage level for SPK_FAULT	With 100-kΩ pullup resistor			0.8	V
I²C CONTROL PORT
C_L(I2C)	Allowable load capacitance for each I²C Line				400	pF
f_SCL(fast)	Support SCL frequency	No wait states, fast mode			400	kHz
f_SCL(slow)	Support SCL frequency	No wait states, slow mode			100	kHz
V_NH	Noise margin at High level for each connected device (including hysteresis)		0.2 × V_DD			V
MCLK AND PLL SPECIFICATIONS
D_MCLK	Allowable MCLK duty cycle		40%		60%
f_MCLK	Supported MCLK frequencies	Up to 50 MHz	128		512	f_S⁽¹⁾
f_PLL	PLL input frequency	Clock divider uses fractional divide D > 0, P = 1	6.7		20	MHz
f_PLL	PLL input frequency	Clock divider uses integer divide D = 0, P = 1	1		20	MHz
SERIAL AUDIO PORT
t_DLY	Required LRCK/FS to SCLK rising edge delay		5			ns
D_SCLK	Allowable SCLK duty cycle		40%		60%
f_S	Supported input sample rates		8		192	kHz
f_SCLK	Supported SCLK frequencies		32		64	f_S⁽¹⁾
f_SCLK	SCLK frequency	Either master mode or slave mode			24.576	MHz
SPEAKER AMPLIFIER (ALL OUTPUT CONFIGURATIONS)
A_{V(SPK_AMP)}	Speaker amplifier gain	SPK_GAIN/FREQ voltage < 3 V, see Adjustable Amplifier Gain and Switching Frequency Selection		20		dBV
A_{V(SPK_AMP)}	Speaker amplifier gain	SPK_GAIN/FREQ voltage > 3.3 V, see Adjustable Amplifier Gain and Switching Frequency Selection		26		dBV
ΔA_{V(SPK_AMP)}	Typical variation of speaker amplifier gain			±1		dBV
f_{SPK_AMP}	Switching frequency of the speaker amplifier	Switching frequency depends on voltage presented at SPK_GAIN/FREQ pin and the clocking arrangement, including the incoming sample rate, see Adjustable Amplifier Gain and Switching Frequency Selection	176.4		768	kHz
K_SVR	Power supply rejection ratio	Injected Noise = 50 Hz to 60 Hz, 200 mV_P-P, Gain = 26 dBV, input audio signal = digital zero		60		dB
r_DS(on)	Drain-to-source on resistance of the individual output MOSFETs	V_PVDD = 24 V, I_{(SPK_OUT)} = 500 mA, T_J = 25°C, includes PVDD/PGND pins, leadframe, bondwires and metallization layers.		90		mΩ
r_DS(on)		V_PVDD = 24 V, I_{(SPK_OUT)} = 500 mA, T_J = 25°C		90		mΩ
OCE_THRES	SPK_OUTxx Overcurrent Error Threshold			7.5		A
OTE_THRES	Overtemperature Error Threshold			150		°C
OCE_CLRTIME	Time required to clear Overcurrent Error after error condition is removed.			1.3		s
OTE_CLRTIME	Time required to clear Overtemperature Error after error condition is removed.			1.3		s
OVE_THRES(PVDD)	PVDD Overvoltage Error Threshold			27		V
UVE_THRES(PVDD)	PVDD Undervoltage Error Threshold			4.5		V
SPEAKER AMPLIFIER (STEREO BTL)
\|V_OS\|	Amplifier offset voltage	Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 20 dBV gain, V_PVDD = 12 V		2	10	mV
\|V_OS\|	Amplifier offset voltage	Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 26 dBV gain, V_PVDD = 24 V		6	15	mV
I_CN(SPK)	Idle channel noise	V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 8 Ω, A-Weighted		56		µV_RMS
		V_PVDD = 15 V, SPK_GAIN = 20 dBV, R_SPK = 8 Ω, A-Weighted		58
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, A-Weighted		86
		V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, A-Weighted		88
P_O(SPK)	Output Power (Per Channel)	V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted		15		W
		V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted		20
		V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, THD+N = 0.1%		28
		V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 8 Ω, THD+N = 0.1%		20
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, R_SPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted		18
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, THD+N = 0.1%		18
		V_PVDD = 15 V, SPK_GAIN = 26 dBV, R_SPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted		18
		V_PVDD = 15 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, THD+N = 0.1%		12
SNR	Signal-to-noise ratio (referenced to 0 dBFS input signal)	V_PVDD = 15 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, A-Weighted, –120 dBFS Input		104		dB
		V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 8 Ω, A-Weighted, –120 dBFS Input		104
		V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, A-Weighted, –120 dBFS Input		106
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, A-Weighted, –120 dBFS Input		105
THD+N_SPK	Total harmonic distortion and noise	V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 4 Ω, P_O = 1 W		0.011%
		V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 8 Ω, P_O = 1 W		0.007%
		V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 4 Ω, P_O = 1 W		0.02%
		V_PVDD = 15 V, SPK_GAIN = 26 dBV, R_SPK = 4 Ω, P_O = 1 W		0.015%
		V_PVDD = 15 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, P_O = 1 W		0.01%
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, R_SPK = 4 Ω, P_O = 1 W		0.017%
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, P_O = 1 W		0.015%
		V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, P_O = 1 W		0.017%
X-talk_SPK	Cross-talk (worst case between left-to-right and right-to-left coupling)	V_PVDD = 15 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, Input Signal 250 mVrms, 1-kHz Sine, across f(S)		–88		dB
		V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 8 Ω, Input Signal 250 mVrms, 1-kHz Sine, across f(S)		–97
		V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, Input Signal 250 mVrms, 1-kHz Sine, across f(S)		–88
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, Input Signal 250 mVrms, 1-kHz Sine, across f(S)		–88
SPEAKER AMPLIFIER (MONO PBTL)
\|V_OS\|	Amplifier offset voltage	Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 20 dBV gain, V_PVDD= 12 V		0.5	8	mV
\|V_OS\|	Amplifier offset voltage	Measured differentially with zero input data, SPK_GAIN/FREQ pin configured for 26 dBV gain, V_PVDD = 24 V		1	14	mV
I_CN	Idle channel noise	V_PVDD = 15 V, SPK_GAIN = 20 dBV, RSPK = 8 Ω, A-Weighted		58		µV_RMS
		V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 8 Ω, A-Weighted		57
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, RSPK = 8 Ω, A-Weighted		85
		V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, A-Weighted		85
P_O	Output Power (Per Channel)	V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 2 Ω, THD+N = 0.1%, Unless otherwise noted		40		W
		V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted		56
		V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, THD+N = 0.1%		34
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, R_SPK = 2 Ω, THD+N = 0.1%, Unless otherwise noted		40
		V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 8 Ω, THD+N = 0.1%		8
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, R_SPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted		36
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, THD+N = 0.1%		21.3
		V_PVDD = 15 V, SPK_GAIN = 26 dBV, R_SPK = 2 Ω, THD+N = 0.1%, Unless otherwise noted		36
		V_PVDD = 15 V, SPK_GAIN = 26 dBV, R_SPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted		24
		V_PVDD = 15 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, THD+N = 0.1%		13.5
		V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 2 Ω, THD+N = 0.1%, Unless otherwise noted		30
		V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 4 Ω, THD+N = 0.1%, Unless otherwise noted		15
SNR	Signal-to-noise ratio (referenced to 0 dBFS input signal)	V_PVDD = 15 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, A-Weighted, –120 dBFS Input		104		dB
		V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 8 Ω, A-Weighted, –120 dBFS Input		104
		V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, A-Weighted, –120 dBFS Input		107
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, A-Weighted, –120 dBFS Input		105
THD+N	Total harmonic distortion and noise	V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 4 Ω, P_O = 1 W		0.013%
		V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 8 Ω, P_O = 1 W		0.007%
		V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 4 Ω, P_O = 1 W		0.02%
		V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 2 Ω, P_O = 1 W		0.028%
		V_PVDD = 24 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, P_O = 1 W		0.018%
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, R_SPK = 4 Ω, P_O = 1 W		0.017%
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, R_SPK = 2 Ω, P_O = 1 W		0.027%
		V_PVDD = 15 V, SPK_GAIN = 26 dBV, R_SPK = 4 Ω, P_O = 1 W		0.016%
		V_PVDD = 15 V, SPK_GAIN = 26 dBV, R_SPK = 2 Ω, P_O = 1 W		0.03%
		V_PVDD = 15 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, P_O = 1 W		0.01%
		V_PVDD = 12 V, SPK_GAIN = 20 dBV, R_SPK = 2 Ω, P_O = 1 W		0.03%
		V_PVDD = 19 V, SPK_GAIN = 26 dBV, R_SPK = 8 Ω, P_O = 1 W		0.012%

(1) A unit of f_S indicates that the specification is the value listed in the table multiplied by the sample rate of the audio used in the TAS5756M device.

(2) DVDD referenced digital pins include: ADR0, ADR1, GPIO0, GPIO1, GPIO2, LRCK/FS, MCLK, SCL, SCLK, SDA, SDIN, and SPK_MUTE.

7.6 MCLK Timing

See Figure 18.

		MIN	MAX	UNIT
t_MCLK	MCLK period	20	1000	ns
t_MCLKH	MCLK pulse width, high	9		ns
t_MCLKL	MCLK pulse width, low	9		ns

7.7 Serial Audio Port Timing – Slave Mode

See Figure 19.

		MIN	MAX	UNIT
f_SCLK	SCLK frequency	1.024		MHz
t_SCLK	SCLK period	40		ns
t_SCLKL	SCLK pulse width, low	16		ns
t_SCLKH	SCLK pulse width, high	16		ns
t_SL	SCLK rising to LRCK/FS edge	8		ns
t_LS	LRCK/FS Edge to SCLK rising edge	8		ns
t_SU	Data setup time, before SCLK rising edge	8		ns
t_DH	Data hold time, after SCLK rising edge	8		ns
t_DFS	Data delay time from SCLK falling edge		15	ns

7.8 Serial Audio Port Timing – Master Mode

See Figure 20.

		MIN	MAX	UNIT
t_SCLK	SCLK period	40		ns
t_SCLKL	SCLK pulse width, low	16		ns
t_SCLKH	SCLK pulse width, high	16		ns
t_LRD	LRCK/FS delay time from to SCLK falling edge	–10	20	ns
t_SU	Data setup time, before SCLK rising edge	8		ns
t_DH	Data hold time, after SCLK rising edge	8		ns
t_DFS	Data delay time from SCLK falling edge		15	ns

7.9 I²C Bus Timing – Standard

		MIN	MAX	UNIT
f_SCL	SCL clock frequency		100	kHz
t_BUF	Bus free time between a STOP and START condition	4.7		µs
t_LOW	Low period of the SCL clock	4.7		µs
t_HI	High period of the SCL clock	4		µs
t_RS-SU	Setup time for (repeated) START condition	4.7		µs
t_S-HD	Hold time for (repeated) START condition	4		µs
t_D-SU	Data setup time	250		ns
t_D-HD	Data hold time	0	900	ns
t_SCL-R	Rise time of SCL signal	20 + 0.1C_B	1000	ns
t_SCL-R1	Rise time of SCL signal after a repeated START condition and after an acknowledge bit	20 + 0.1C_B	1000	ns
t_SCL-F	Fall time of SCL signal	20 + 0.1C_B	1000	ns
t_SDA-R	Rise time of SDA signal	20 + 0.1C_B	1000	ns
t_SDA-F	Fall time of SDA signal	20 + 0.1C_B	1000	ns
t_P-SU	Setup time for STOP condition	4		µs

7.10 I²C Bus Timing – Fast

See Figure 21.

		MIN	MAX	UNIT
f_SCL	SCL clock frequency		400	kHz
t_BUF	Bus free time between a STOP and START condition	1.3		µs
t_LOW	Low period of the SCL clock	1.3		µs
t_HI	High period of the SCL clock	600		ns
t_RS-SU	Setup time for (repeated)START condition	600		ns
t_RS-HD	Hold time for (repeated)START condition	600		ns
t_D-SU	Data setup time	100		ns
t_D-HD	Data hold time	0	900	ns
t_SCL-R	Rise time of SCL signal	20 + 0.1C_B	300	ns
t_SCL-R1	Rise time of SCL signal after a repeated START condition and after an acknowledge bit	20 + 0.1C_B	300	ns
t_SCL-F	Fall time of SCL signal	20 + 0.1C_B	300	ns
t_SDA-R	Rise time of SDA signal	20 + 0.1C_B	300	ns
t_SDA-F	Fall time of SDA signal	20 + 0.1C_B	300	ns
t_P-SU	Setup time for STOP condition	600		ns
t_SP	Pulse width of spike suppressed		50	ns

7.11 SPK_MUTE Timing

See Figure 22.

		MIN	MAX	UNIT
t_r	Rise time		20	ns
t_f	Fall time		20	ns

7.12 Power Dissipation

V_PVDD (V)	SPK_GAIN⁽¹⁾⁽²⁾⁽³⁾ (dBV)	f_{SPK_AMP} (kHz)	STATE OF OPERATION	R_SPK (Ω)	I_PVDD⁽⁴⁾ (mA)	I_DVDD⁽⁵⁾ (mA)	P_DISS (W)
7.4	20	384	Idle	4	21.3	35	0.273
				6	21.33	35	0.273
				8	21.3	35	0.273
			Mute	4	21.33	35	0.273
				6	21.34	35	0.273
				8	21.36	35	0.274
			Standby	4	2.08	17	0.071
				6	2.11	17	0.072
				8	2.17	17	0.072
			Powerdown	4	2.03	1	0.018
				6	2.04	1	0.018
				8	2.06	1	0.019
		768	Idle	4	27.48	35	0.319
				6	27.49	35	0.319
				8	24.46	35	0.297
			Mute	4	27.5	35	0.319
				6	27.51	35	0.319
				8	27.52	35	0.319
			Standby	4	2.04	17	0.071
				6	2.08	17	0.071
				8	2.11	17	0.072
			Powerdown	4	2.06	1	0.019
				6	2.07	1	0.019
				8	2.08	1	0.019
11.1	20	384	Idle	4	24.33	35	0.386
				6	24.32	35	0.385
				8	24.36	35	0.386
			Mute	4	24.36	35	0.386
				6	24.32	35	0.385
				8	24.37	35	0.386
			Standby	4	3.58	17	0.096
				6	3.57	17	0.096
				8	3.58	17	0.096
			Powerdown	4	3.52	1	0.042
				6	3.52	1	0.042
				8	3.54	1	0.043
		768	Idle	4	30.7	35	0.456
				6	30.65	35	0.456
				8	30.67	35	0.456
			Mute	4	3.072	35	0.150
				6	30.69	35	0.456
				8	30.69	35	0.456
			Standby	4	3.54	17	0.095
				6	3.54	17	0.095
				8	3.58	17	0.096
			Powerdown	4	3.53	1	0.042
				6	3.53	1	0.042
				8	3.55	1	0.043
12	20	384	Idle	4	25.07	35	0.416
				6	25.08	35	0.416
				8	25.1	35	0.417
			Mute	4	25.12	35	0.417
				6	25.08	35	0.416
				8	25.11	35	0.417
			Standby	4	3.92	17	0.103
				6	3.93	17	0.103
				8	3.94	17	0.103
			Powerdown	4	3.87	1	0.050
				6	3.85	1	0.050
				8	3.87	1	0.050
		768	Idle	4	31.31	35	0.491
				6	31.29	35	0.491
				8	31.31	35	0.491
			Mute	4	31.31	35	0.491
				6	31.33	35	0.491
				8	31.32	35	0.491
			Standby	4	3.88	17	0.103
				6	3.9	17	0.103
				8	3.91	17	0.103
			Powerdown	4	3.89	1	0.050
				6	3.91	1	0.050
				8	3.88	1	0.050
15	26	384	Idle	4	27.94	35	0.535
				6	27.91	35	0.534
				8	27.75	35	0.532
			Mute	4	27.98	35	0.535
				6	27.94	35	0.535
				8	27.88	35	0.534
			Standby	4	5.09	17	0.132
				6	5.12	17	0.133
				8	5.19	17	0.134
			Powerdown	4	5.02	1	0.079
				6	5.06	1	0.079
				8	5.14	1	0.080
		768	Idle	4	33.05	35	0.611
				6	33.03	35	0.611
				8	33.08	35	0.612
			Mute	4	33.03	35	0.611
				6	33.04	35	0.611
				8	33.05	35	0.611
			Standby	4	5.07	17	0.132
				6	5.09	17	0.132
				8	5.14	17	0.133
			Powerdown	4	5.02	1	0.079
				6	5.04	1	0.079
				8	5.09	1	0.080
19.6	26	384	Idle	4	32.27	35	0.748
				6	32.19	35	0.746
				8	32.08	35	0.744
			Mute	4	32.27	35	0.748
				6	32.24	35	0.747
				8	32.22	35	0.747
			Standby	4	6.95	17	0.192
				6	6.93	17	0.192
				8	7	17	0.193
			Powerdown	4	6.89	1	0.138
				6	6.9	1	0.139
				8	6.96	1	0.140
		768	Idle	4	34.99	35	0.801
				6	34.95	35	0.801
				8	34.97	35	0.801
			Mute	4	34.96	35	0.801
				6	34.98	35	0.801
				8	34.96	35	0.801
			Standby	4	6.93	17	0.192
				6	6.93	17	0.192
				8	6.98	17	0.193
			Powerdown	4	6.84	1	0.137
				6	6.89	1	0.138
				8	6.9	1	0.139
24	26	384	Idle	4	36.93	35	1.002
				6	36.87	35	1.000
				8	36.77	35	0.998
			Mute	4	36.94	35	1.002
				6	36.89	35	1.001
				8	36.85	35	1.000
			Standby	4	8.73	17	0.266
				6	8.72	17	0.265
				8	8.71	17	0.265
			Powerdown	4	8.64	1	0.211
				6	8.66	1	0.211
				8	8.69	1	0.212
		768	Idle	4	36.84	35	1.000
				6	36.86	35	1.000
				8	36.83	35	0.999
			Mute	4	36.85	35	1.000
				6	36.84	35	1.000
				8	36.82	35	0.999
			Standby	4	8.66	17	0.264
				6	8.68	17	0.264
				8	8.71	17	0.265
			Powerdown	4	8.63	1	0.210
				6	8.64	1	0.211
				8	8.65	1	0.211

(1) Mute: P0-R3-B0,B5 = 1

(2) Standby: P0-R2-B5 = 1

(3) P0-R2-B0 = 1

(4) I_PVDD refers to all current that flows through the PVDD supply for the DUT. Any other current sinks not directly related to the DUT current draw were removed.

(5) I_DVDD refers to all current that flows through the DVDD (3.3-V) supply for the DUT. Any other current sinks not directly related to the DUT current draw were removed.

7.13 Typical Characteristics

All performance plots were taken using the TAS5754M-56MEVM at room temperature, unless otherwise noted. The term Traditional LC filter refers to the output filter that is present by default on the EVM. For Filterless measurements, the on-board LC filter was removed and an Audio Precision AUX-025 measurement filter was used to take the measurements.

Table 1. Quick Reference Table

OUTPUT CONFIGURATIONS	PLOT TITLE	FIGURE NUMBER
Bridge Tied Load (BTL) Configuration Curves	Output Power vs PVDD	Figure 23
	THD+N vs Frequency, V_PVDD = 12 V	Figure 24
	THD+N vs Frequency, V_PVDD = 15 V	Figure 25
	THD+N vs Frequency, V_PVDD = 18 V	Figure 26
	THD+N vs Frequency, V_PVDD = 24 V	Figure 27
	THD+N vs Power, V_PVDD = 12 V	Figure 28
	THD+N vs Power, V_PVDD = 15 V	Figure 29
	THD+N vs Power, V_PVDD = 18 V	Figure 30
	THD+N vs Power, V_PVDD = 24 V	Figure 31
	Idle Channel Noise vs PVDD	Figure 32
	Efficiency vs Output Power	Figure 33
	Idle Current Draw (Filterless) vs PVDD	Figure 34
	Idle Current Draw (Traditional LC Filter) vs PVDD	Figure 35
	Crosstalk vs. Frequency	Figure 36
	PVDD PSRR vs Frequency	Figure 37
	DVDD PSRR vs Frequency	Figure 38
	AVDD PSRR vs Frequency	Figure 39
	CPVDD PSRR vs Frequency	Figure 40
	Powerdown Current Draw vs PVDD	Figure 41
Parallel Bridge Tied Load (PBTL) Configuration	Output Power vs PVDD	Figure 42
	THD+N vs Frequency, V_PVDD = 12 V	Figure 43
	THD+N vs Frequency, V_PVDD = 15 V	Figure 44
	THD+N vs Frequency, V_PVDD = 18 V	Figure 45
	THD+N vs Frequency, V_PVDD = 24 V	Figure 46
	THD+N vs Power, V_PVDD = 12 V	Figure 47
	THD+N vs Power, V_PVDD = 15 V	Figure 48
	THD+N vs Power, V_PVDD = 18 V	Figure 49
	THD+N vs Power, V_PVDD = 24 V	Figure 50
	Idle Channel Noise vs PVDD	Figure 51
	Efficiency vs Output Power	Figure 52
	Idle Current Draw (filterless) vs PVDD	Figure 57
	Idle Current Draw (traditional LC filter) vs PVDD	Figure 58
	PVDD PSRR vs Frequency	Figure 53
	DVDD PSRR vs Frequency	Figure 54
	AVDD PSRR vs Frequency	Figure 55
	CPVDD PSRR vs Frequency	Figure 56
	Powerdown Current Draw vs PVDD	Figure 59

7.13.1 Bridge Tied Load (BTL) Configuration Curves

Return to Quick Reference Table.

A_{V(SPK_AMP)} = 26 dBV

Figure 23. Output Power vs PVDD – BTL

A_{V(SPK_AMP)} = 20 dBV

P_O = 1 W

V_PVDD = 15 V

Figure 25. THD+N vs Frequency – BTL

A_{V(SPK_AMP)}
= 26 dBV

P_O = 1 W

V_PVDD = 24 V

Figure 27. THD+N vs Frequency – BTL

A_{V(SPK_AMP)}
= 20 dBV

Input Signal = 1 kHz Sine

V_PVDD = 15 V

Figure 29. THD + N vs Power – BTL

A_{V(SPK_AMP)} = 26 dBV

P_O = 1 W

V_PVDD = 24 V

Figure 31. THD + N vs Power – BTL

TAS5756M C007_BTLEffvPo12V15V18V24V8R.png

R_SPK = 8 Ω

Figure 33. Efficiency vs Output Power – BTL

f_{SPK_AMP} = 768 kHz

R_SPK = 8 Ω

Figure 35. Idle Current Draw
(Traditional LC Filter) vs PVDD – BTL

TAS5756M C009_BTLPVDDPSRRvFreq24V4R6R8.png

A_{V(SPK_AMP)} = 26 dBV	Supply Noise = 250 mV
V_PVDD = 24 V	Sine Input

Figure 37. PVDD PSRR vs Frequency – BTL

A_{V(SPK_AMP)} = 26 dBV	Supply Noise = 250 mV
V_PVDD = 24 V	R_SPK = 8 Ω

Figure 39. AVDD PSRR vs Frequency – BTL

A_{V(SPK_AMP)} = 26 dBV

f_{SPK_AMP} = 786 kHz

Figure 41. Powerdown Current Draw vs PVDD – BTL

A_{V(SPK_AMP)} = 20 dBV

P_O = 1 W

V_PVDD = 12 V

Figure 24. THD+N vs Frequency – BTL

A_{V(SPK_AMP)} = 20 dBV

P_O = 1 W

V_PVDD = 18 V

Figure 26. THD+N vs Frequency – BTL

A_{V(SPK_AMP)}
= 20 dBV

Input Signal = 1 kHz Sine

V_PVDD = 12 V

Figure 28. THD + N vs Power – BTL

A_{V(SPK_AMP)}
= 26 dBV

Input Signal = 1 kHz Sine

V_PVDD = 18 V

Figure 30. THD + N vs Power – BTL

A_{V(SPK_AMP)} = 20 dBV

f_{SPK_AMP} = 384 kHz

R_SPK = 8 Ω

Figure 32. Idle Channel Noise vs PVDD – BTL

TAS5756M C013_BTLIdleFltrlssv4p5to24V8R.png

f_{SPK_AMP} = 768 kHz

R_SPK = 8 Ω

Figure 34. Idle Current Draw (Filterless) vs V_PVDD – BTL

TAS5756M C008_BTLXtlkvFreq24V1W4R6R8R.png

A_{V(SPK_AMP)} = 26 dBV

Sine Input

V_PVDD = 24 V

Figure 36. Crosstalk vs Frequency – BTL

A_{V(SPK_AMP)} = 26 dBV	Supply Noise = 250 mV
V_PVDD = 24 V	R_SPK = 8 Ω

Figure 38. DVDD PSRR vs Frequency – BTL

TAS5756M C012_BTLCPVDDPSRRvFreq24V8R.png

A_{V(SPK_AMP)} = 26 dBV	Supply Noise = 250 mV
V_PVDD = 24 V	Sine Input

Figure 40. CPVDD PSRR vs Frequency – BTL

7.13.2 Parallel Bridge Tied Load (PBTL) Configuration

Return to Quick Reference Table.

A_{V(SPK_AMP)} = 26 dBV

Measured on TAS5754/6 EVM

Figure 42. Output Power vs PVDD – PBTL

A_{V(SPK_AMP)} = 20 dBV

P_O= 1 W

V_PVDD = 15 V

Figure 44. THD+N vs Frequency – PBTL

A_{V(SPK_AMP)} = 26 dBV

P_O= 1 W

V_PVDD = 24 V

Figure 46. THD+N vs Frequency – PBTL

A_{V(SPK_AMP)} = 20 dBV

P_O= 1 W

V_PVDD = 15 V

Figure 48. THD+N vs Power – PBTL

A_{V(SPK_AMP)} = 20 dBV	P_O= 1 W
V_PVDD = 24 V	Input Signal = 1 kHz Sine

Figure 50. THD+N vs Power – PBTL

TAS5756M C026_PBTLEffvPo12V15V18V24V4R.png

A_{V(SPK_AMP)} = 26 dBV

I_LOAD= xA

V_PVDD = 24 V

Figure 52. Efficiency vs Output Power – PBTL

A_{V(SPK_AMP)} = 26 dBV	R_SPK = 8 Ω
V_PVDD = 24 V	Supply Noise = 250 mV

Figure 54. DVDD PSRR vs Frequency – PBTL

TAS5756M C030_PBTLCPVDDPSRRvFreq24V2R.png

A_{V(SPK_AMP)} = 26 dBV	Sine Input
V_PVDD = 24 V	Supply Noise = 250 mV

Figure 56. CPVDD PSRR vs Frequency – PBTL

Figure 58. Idle Current Draw
(Traditional LC filter) vs PVDD – PBTL

A_{V(SPK_AMP)} = 20 dBV

P_O= 1 W

V_PVDD = 12 V

Figure 43. THD+N vs Frequency – PBTL

A_{V(SPK_AMP)} = 26 dBV

P_O= 1 W

V_PVDD = 18 V

Figure 45. THD+N vs Frequency – PBTL

A_{V(SPK_AMP)} = 20 dBV

P_O= 1 W

V_PVDD = 12 V

Figure 47. THD+N vs Power – PBTL

A_{V(SPK_AMP)} = 20 dBV	P_O= 1 W
V_PVDD = 18 V	Input Signal = 1 kHz Sine

Figure 49. THD+N vs Power – PBTL

TAS5756M C025_PBTLICNvPVDD4p5to24V4R.png

A_{V(SPK_AMP)}
= 26 dBV

I_LOAD= xA

V_PVDD = 18 V

Figure 51. Idle Channel Noise vs PVDD – PBTL

TAS5756M C027_PBTLPVDDPSRRvFreq24V2R4R6R.png

A_{V(SPK_AMP)} = 26dBV

Sine Input

V_PVDD = 24V

Figure 53. PVDD PSRR vs Frequency – PBTL

TAS5756M C029_PBTLAVDDPSRRvFreq24V2R.png

A_{V(SPK_AMP)} = 26 dBV	R_SPK = 8 Ω
V_PVDD = 24 V	Supply Noise = 250 mV

Figure 55. AVDD PSRR vs Frequency – PBTL

TAS5756M C031_PBTLIdleFltrlssv4p5to24V4R.png

Figure 57. Idle Current Draw (Filterless) vs PVDD – PBTL

A_{V(SPK_AMP)} = 26 dBV

f_{SPK_AMP} = 786 kHz

Figure 59. Powerdown Current Draw vs PVDD – PBTL

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7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 MCLK Timing

7.7 Serial Audio Port Timing – Slave Mode

7.8 Serial Audio Port Timing – Master Mode

7.9 I²C Bus Timing – Standard

7.10 I²C Bus Timing – Fast

7.11 SPK_MUTE Timing

7.12 Power Dissipation

7.13 Typical Characteristics

Table 1. Quick Reference Table

7.13.1 Bridge Tied Load (BTL) Configuration Curves

7.13.2 Parallel Bridge Tied Load (PBTL) Configuration

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7 Specifications

7.1 Absolute Maximum Ratings

7.2 ESD Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

7.6 MCLK Timing

7.7 Serial Audio Port Timing – Slave Mode

7.8 Serial Audio Port Timing – Master Mode

7.9 I2C Bus Timing – Standard

7.10 I2C Bus Timing – Fast

7.11 SPK_MUTE Timing

7.12 Power Dissipation

7.13 Typical Characteristics

Table 1. Quick Reference Table

7.13.1 Bridge Tied Load (BTL) Configuration Curves

7.13.2 Parallel Bridge Tied Load (PBTL) Configuration

7.9 I²C Bus Timing – Standard

7.10 I²C Bus Timing – Fast