9.2.2.2 CLK Pin Rise Time And Fall Time Settings

Electrical Characteristics—Card CLK shows the typical rise and fall time of the clock signal for a 30 pF load. Because most applications will not have a typical 30 pF load, the rise and fall time of the clock signal will need to be calibrated for the board. EMV 4.3 specifies that the rise/fall time on the clock signal shall not be more than 8% of the clock period. It is recommended that the slowest fall time setting that meets the EMV requirement be selected. For systems where multiple clock frequencies will be used, it is recommended that a different fall time setting be used for each clock frequency.