米6体育平台手机版

ZHCSDP5E December 2010 – February 2017 TCA9554A

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DW|16
- MSOI003I
PW|16
- MPDS361A
DBQ|16
- MSOI004H
DB|16
- MPDS507A

散热焊盘机械数据 (封装 | 引脚)

DW|16
- QFND313D

订购信息

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_CC	Supply voltage		–0.5	6	V
V_I	Input voltage⁽²⁾		–0.5	6	V
V_O	Output voltage⁽²⁾		–0.5	6	V
I_IK	Input clamp current	V_I < 0		–20	mA
I_OK	Output clamp current	V_O < 0		–20	mA
I_IOK	Input-output clamp current	V_O < 0 or V_O > V_CC		±20	mA
I_OL	Continuous output low current through a single P-port	V_O = 0 to V_CC		50	mA
I_OH	Continuous output high current through a single P-port	V_O = 0 to V_CC		–50	mA
I_CC	Continuous current through GND by all P-ports, INT, and SDA			250	mA
I_CC	Continuous current through V_CC by all P-ports			–160	mA
T_j(MAX)	Maximum junction temperature			100	°C
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

				MIN	MAX	UNIT
V_CC	Supply voltage			1.65	5.5	V
V_IH	High-level input voltage	SCL, SDA	V_CC = 1.65 V to 5.5 V	0.7 × V_CC	V_CC⁽¹⁾	V
		A2–A0, P7–P0	V_CC = 1.65 V to 2.7 V	0.7 × V_CC	5.5
		A2–A0, P7–P0	V_CC = 3 V to 5.5 V	0.8 × V_CC	5.5
V_IL	Low-level input voltage	SCL, SDA	V_CC = 1.65 V to 5.5 V	–0.5	0.3 × V_CC	V
		A2–A0, P7–P0	V_CC = 1.65 V to 2.7 V	–0.5	0.3 × V_CC
		A2–A0, P7–P0	V_CC = 3 V to 5.5 V	–0.5	0.2 × V_CC
I_OH	High-level output current	Any P-port, P7–P0			–10	mA
I_OL	Low-level output current⁽²⁾	P00–P07, P10–P17	T_j ≤ 65°C		25	mA
			T_j ≤ 85°C		18
			T_j ≤ 100°C		9
		INT, SDA	T_j ≤ 85°C		6
		INT, SDA	T_j ≤ 100°C		3
I_CC	Continuous current through GND	All P-ports P7-P0, INT, and SDA			200	mA
I_CC	Continuous current through V_CC	All P-ports P7-P0			–80	mA
T_A	Operating free-air temperature			–40	85	°C

(1) The SCL and SDA pins shall not be at a higher potential than the supply voltage V_CC in the application, or an increase in leakage current, I_I, will result.

(2) For voltages applied above V_CC, an increase in I_CC will result.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TCA9554A				UNIT
		PW (TSSOP)	DBQ (SSOP)	DB (SSOP)	DW (SOIC)
		16 PINS	16 PINS	16 PINS	16 PINS
R_θJA	Junction-to-ambient thermal resistance	122	121.7	113.2	84.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	56.4	72.9	63.6	48	°C/W
R_θJB	Junction-to-board thermal resistance	67.1	64.2	64	49.1	°C/W
ψ_JT	Junction-to-top characterization parameter	10.8	24.4	21.2	22.7	°C/W
ψ_JB	Junction-to-board characterization parameter	66.5	63.8	63.4	48.7	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		V_CC	MIN	TYP⁽¹⁾	MAX	UNIT
V_IK	Input diode clamp voltage	I_I = –18 mA		1.65 V to 5.5 V	–1.2			V
V_PORR	Power-on reset voltage, V_CC rising	V_I = V_CC or GND, I_O = 0				1.2	1.5	V
V_PORF	Power-on reset voltage, V_CC falling	V_I = V_CC or GND, I_O = 0			0.75	1		V
V_OH	P-port high-level output voltage⁽²⁾	I_OH = –8 mA		1.65 V	1.2			V
				2.3 V	1.8
				3 V	2.6
				4.5 V	4.1
		I_OH = –10 mA		1.65 V	1.1
				2.3 V	1.7
				3 V	2.5
				4.5 V	4
I_OL	SDA⁽⁴⁾	V_OL = 0.4 V		1.65 V to 5.5 V	3	11		mA
	P port⁽³⁾	V_OL = 0.5 V		1.65 V	8	10
				2.3 V	8	13
				3 V	8	15
				4.5 V	8	17
		V_OL = 0.7 V		1.65 V	10	14
				2.3 V	10	17
				3 V	10	20
				4.5 V	10	24
	INT ⁽⁵⁾	V_OL = 0.4 V		1.65 V to 5.5 V	3	7
I_I	SCL, SDA	V_I = V_CC or GND		1.65 V to 5.5 V			±1	μA
I_I	A2–A0	V_I = V_CC or GND		1.65 V to 5.5 V			±1	μA
I_IH	P port	V_I = V_CC		1.65 V to 5.5 V			1	μA
I_IL	P port	V_I = GND		1.65 V to 5.5 V			–100	μA
I_CC	Operating mode	V_I = V_CC or GND, I_O = 0, I/O = inputs, f_SCL = 400 kHz, no load		5.5 V		34		μA
				3.6 V		15
				2.7 V		9
				1.95 V		5
	Standby mode	I/O = inputs, f_SCL = 0 kHz	V_I = V_CC	5.5 V		1.9	3.5
				3.6 V		1.1	1.8
				2.7 V		1	1.6
				1.95 V		0.4	1
			V_I = GND	5.5 V		0.45	0.7	mA
				3.6 V		0.3	0.6
				2.7 V		0.23	0.5
				1.95 V		0.23	0.5
C_i	SCL	V_I = V_CC or GND		1.65 V to 5.5 V		3	8	pF
C_io	SDA	V_IO = V_CC or GND		1.65 V to 5.5 V		5.5	9.5	pF
C_io	P port	V_IO = V_CC or GND		1.65 V to 5.5 V		8	9.5	pF

(1) All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V V_CC) and T_A = 25°C.

(2) Each P-port I/O configured as a high output must be externally limited to a maximum of 10 mA, and the total current sourced by all I/Os (P-ports P7-P0) through V_CC must be limited to a maximum current of 80 mA.

(3) Each P-port I/O configured as a low output must be externally limited to a maximum of 25 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA.

(4) The SDA pin must be externally limited to a maximum of 12 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA.

(5) The INT pin must be externally limited to a maximum of 7 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA.

6.6 I²C Interface Timing Requirements

over operating free-air temperature range (unless otherwise noted) (see Figure 11)

			MIN	MAX	UNIT
STANDARD MODE
f_scl	I²C clock frequency		0	100	kHz
t_sch	I²C clock high time		4		µs
t_scl	I²C clock low time		4.7		µs
t_sp	I²C spike time			50	ns
t_sds	I²C serial-data setup time		250		ns
t_sdh	I²C serial-data hold time		0		ns
t_icr	I²C input rise time			1000	ns
t_icf	I²C input fall time			300	ns
t_ocf	I²C output fall time	10-pF to 400-pF bus		300	ns
t_buf	I²C bus free time between Stop and Start		4.7		µs
t_sts	I²C Start or repeated Start condition setup		4.7		µs
t_sth	I²C Start or repeated Start condition hold		4		µs
t_sps	I²C Stop condition setup		4		µs
t_vd(data)	Valid data time	SCL low to SDA output valid		3.45	ns
t_vd(ack)	Valid data time of ACK condition	ACK signal from SCL low to SDA (out) low		3.45	µs
C_b	I²C bus capacitive load			400	pF
FAST MODE
f_scl	I²C clock frequency		0	400	kHz
t_sch	I²C clock high time		0.6		µs
t_scl	I²C clock low time		1.3		µs
t_sp	I²C spike time			50	ns
t_sds	I²C serial-data setup time		100		ns
t_sdh	I²C serial-data hold time		0		ns
t_icr	I²C input rise time		20	300	ns
t_icf	I²C input fall time		20 × (V_DD/ 5.5 V)	300	ns
t_ocf	I²C output fall time	10-pF to 400-pF bus	20 × (V_DD/ 5.5 V)	300	ns
t_buf	I²C bus free time between Stop and Start		1.3		µs
t_sts	I²C Start or repeated Start condition setup		0.6		µs
t_sth	I²C Start or repeated Start condition hold		0.6		µs
t_sps	I²C Stop condition setup		0.6		µs
t_vd(data)	Valid data time	SCL low to SDA output valid		0.9	ns
t_vd(ack)	Valid data time of ACK condition	ACK signal from SCL low to SDA (out) low		0.9	µs
C_b	I²C bus capacitive load			400	pF

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) (see Figure 12 and Figure 13)

PARAMETER		FROM (INPUT)	TO (OUTPUT)	MIN	MAX	UNIT
STANDARD MODE and FAST MODE
t_iv	Interrupt valid time	P port	INT		4	µs
t_ir	Interrupt reset delay time	SCL	INT		4	µs
t_pv	Output data valid	SCL	P7–P0		350	ns
t_ps	Input data setup time	P port	SCL	100		ns
t_ph	Input data hold time	P port	SCL	1		μs