ZHCSQV1C March 2020 – December 2022 TCAN1463-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|---|---|
| Driver Characteristics | ||||||||
| tprop(TxD-busdom) | Propagation delay time, high-to-low TXD edge to bus dominant (recessive to dominant) | RL = 60 Ω, CL = 100 pF, RCM = open See Figure 8-4 |
80 | ns | ||||
| tprop(TxD-busrec) | Propagation delay time, low-to-high TXD edge to bus recessive (dominant to recessive) | 80 | ns | |||||
| tsk(p) | Pulse skew (|tprop(TxD-busdom) - tprop(TxD-busrec)|) | RL = 60 Ω, CL = 100 pF, RCM = open See Figure 8-4 |
3 | ns | ||||
| tR | Differential output signal rise time | 25 | ns | |||||
| tF | Differential output signal fall time | 25 | ns | |||||
| tTXDDTO | Dominant timeout | TXD = 0 V, RL = 60 Ω, CL = open See Figure 8-7 |
1.2 | 3.8 | ms | |||
| Receiver Characteristics | ||||||||
| tprop(busdom-RxD) | Propagation delay time, bus dominant input to RxD low output | CL(RXD) = 15 pF See Figure 8-5 |
110 | ns | ||||
| tprop(busrec-RxD) | Propagation delay time, bus to recessive input to RXD high output | 110 | ns | |||||
| tR | Output signal rise time (RXD) | CL(RXD) = 15 pF See Figure 8-5 |
3 | ns | ||||
| tF | Output signal fall time (RXD) | 3 | ns | |||||
| tBUSDOM | Dominant time out | RL = 60 Ω, CL = open See Figure 8-5 |
1.4 | 3.8 | ms | |||
| CAN FD Characteristics | ||||||||
| tBIT(BUS)(1) | Bit time on CAN bus output pins with tBIT(TXD) = 500 ns | RL = 60 Ω, CL1 = open, CL2 = 100 pF, CL(RXD) = 15 ΔtREC = tBIT(RXD) - tBIT(BUS) See Figure 8-6 |
490 | 510 | ns | |||
| Bit time on CAN bus output pins with tBIT(TXD) = 200 ns | 190 | 210 | ns | |||||
| Bit time on CAN bus output pins with tBIT(TXD) = 125 ns(2) | 115 | 135 | ns | |||||
| tBIT(RXD)(1) | Bit time on RXD output pins with tBIT(TXD) = 500 ns | 470 | 520 | ns | ||||
| Bit time on RXD output pins with tBIT(TXD) = 200 ns | 170 | 210 | ns | |||||
| Bit time on RXD output pins with tBIT(TXD) = 125 ns(2) | 95 | 135 | ns | |||||
| ΔtREC(1) | Receiver timing symmetry with tBIT(TXD) = 500 ns | –20 | 15 | ns | ||||
| Receiver timing symmetry with tBIT(TXD) = 200 ns | –20 | 15 | ns | |||||
| Receiver timing symmetry with tBIT(TXD) = 125 ns(3) | –20 | 15 | ns | |||||
| Signal Improvement Characteristics | ||||||||
| tSIC_TX_base | Signal improvement time TX-based | Time from rising edge of the TxD signal to the end of the signal improvement phase | 530 | ns | ||||
| ΔtBit(Bus) | Transmitted bit width variation | Bus recessive bit length variation relative to TxD bit length, see Figure 8-6 ΔtBit(Bus) = tBit(Bus) - tBit(TxD) | –10 | 10 | ns | |||
| ΔtBIT(RxD) | Received bit width variation | RxD recessive bit length variation relative to TXD bit length, see Figure 8-6 ΔtBit(RxD) = tBit(RxD) - tBit(TxD) | –30 | 20 | ns | |||
| ΔtREC | Receiver timing symmetry | RXD recessive bit length variation relative to bus bit length, see Figure 8-6 ΔtREC = tBit(RxD) - tBit(Bus) | –20 | 15 | ns | |||