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ZHCSJ48F December 2016 – December 2018 TDA2P-ABZ

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ABZ|760
- MPBGAN4A

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5.5.2 Voltage And Core Clock Specifications

Table 5-3 shows the recommended OPP per voltage domain.

Table 5-3 Voltage Domains Operating Performance Points

DOMAIN	CONDITION	OPP_LOW			OPP_NOM			OPP_OD			OPP_HIGH
DOMAIN	CONDITION	MIN ^⁽²⁾	NOM ^⁽¹⁾	MAX ^⁽²⁾	MIN ^⁽²⁾	NOM ^⁽¹⁾	MAX ^⁽²⁾	MIN ^⁽²⁾	NOM ^⁽¹⁾	MAX ^⁽²⁾	MIN ^⁽²⁾	NOM ^⁽¹⁾	MAX DC ^⁽³⁾	MAX ^⁽²⁾
VD_CORE (V)	BOOT (Before AVS is enabled) ^⁽⁴⁾	Not Applicable			1.11	1.15	1.2	Not Applicable			Not Applicable
VD_CORE (V)	After AVS is enabled ^⁽⁴⁾	Not Applicable			AVS^⁽⁵⁾ – 3.5%	AVS^⁽⁵⁾	1.2	Not Applicable			Not Applicable
VD_MPU (V)	BOOT (Before AVS is enabled) ^⁽⁴⁾	Not Applicable			1.11	1.15	1.2	Not Applicable			Not Applicable
VD_MPU (V)	After AVS is enabled ^⁽⁴⁾	AVS Voltage ^⁽⁵⁾ – 3.5%	AVS Voltage ^⁽⁵⁾	AVS Voltage ^⁽⁵⁾ + 5%	AVS Voltage^⁽⁵⁾ – 3.5%	AVS Voltage^⁽⁵⁾	1.2	AVS Voltage^⁽⁵⁾ – 3.5%	AVS Voltage^⁽⁵⁾	AVS Voltage^⁽⁵⁾ + 5%	AVS Voltage^⁽⁵⁾ – 3.5%	AVS Voltage^⁽⁵⁾	AVS Voltage^⁽⁵⁾ + 2%	AVS Voltage^⁽⁵⁾ + 5%
VD_RTC (V) ^⁽⁶⁾	-	Not Applicable			0.84	0.88 to 1.06	1.2	Not Applicable			Not Applicable
Others (V)	BOOT (Before AVS is enabled) ^⁽⁴⁾	Not Applicable			1.02	1.06	1.2	Not Applicable			Not Applicable
Others (V)	After AVS is enabled ^⁽⁴⁾	Not Applicable			AVS Voltage^⁽⁵⁾ – 3.5%	AVS Voltage^⁽⁵⁾	1.2	AVS Voltage^⁽⁵⁾ – 3.5%	AVS Voltage^⁽⁵⁾	AVS Voltage^⁽⁵⁾ + 5%	AVS Voltage^⁽⁵⁾ – 3.5%	AVS Voltage^⁽⁵⁾	AVS Voltage^⁽⁵⁾ + 2%	AVS Voltage^⁽⁵⁾ + 5%

In a typical implementation, the power supply should target the NOM voltage.
The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH (Power-On Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On Hours), and device power.
The AVS voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the STD_FUSE_OPP. For information about STD_FUSE_OPP Registers address, please refer to Control Module section of the Device TRM. The power supply should be adjustable over the following ranges for each required OPP:
- OPP_LOW for MPU: 0.85 V - 1.15 V
- OPP_NOM for MPU: 0.85 V - 1.15 V
- OPP_NOM for CORE and Others: 0.85 V - 1.15 V
- OPP_OD: 0.885 V - 1.15 V
- OPP_HIGH: 0.95 V - 1.25 V
The AVS voltages will be within the above specified ranges.
VD_RTC can optionally be tied to VD_CORE and operate at the VD_CORE AVS voltages.
The power supply must be programmed with the AVS voltages for the MPU and the CORE voltage domain, either just after the ROM boot or at the earliest possible time in the secondary boot loader before there is significant activity seen on these domains.

Table 5-4 describes the standard processor clocks speed characteristics vs OPP of the device.

Table 5-4 Supported OPP vs Max Frequency^⁽¹⁾^⁽²⁾

DESCRIPTION	OPP_LOW	OPP_NOM	OPP_OD	OPP_HIGH
DESCRIPTION	Max Freq. (MHz)	Max Freq. (MHz)	Max Freq. (MHz)	Max Freq. (MHz)
VD_MPU
MPU_CLK	750	1000	1176	1176
VD_DSPEVE
DSP_CLK	N/A	600	700	750
EVE_FCLK	N/A	535	650	650
ISP_CLK	N/A	355	355	532
VD_IVA
IVA_GCLK	N/A	388.3	430	532
VD_GPU
GPU_CLK	N/A	425.6	500	532
VD_CORE
CORE_IPUx_CLK	N/A	212.8	N/A	N/A
L3_CLK	N/A	266	N/A	N/A
DDR2	N/A	400 (DDR2-800)	N/A	N/A
DDR3 / DDR3L	N/A	667 (DDR3-1333)	N/A	N/A
VD_RTC
RTC_FCLK	N/A	0.034	N/A	N/A

N/A in this table stands for Not Applicable.
Maximum supported frequency is limited according to the Device Speed Grade (see Table 5-1).