10.1.1.1.1 Design Requirements

For this design example, use the parameters listed in Table 8 as the input parameters.

10.1.1.1.2 Detailed Design Procedure

The THS3217 is well suited for high-speed, low-distortion arbitrary waveform generator (AWG) applications commonly used in laboratory equipment. In this typical application, a high-speed, complementary-current-output DAC is used to drive the D2S. The OPS of the THS3217 easily drives a 100-MHz, 2.5-V_PP signal into a matched 50-Ω load. When a larger output signal is required, consider using the THS3091 as the final driver stage.

A passive RLC filter is commonly used on DAC outputs to reduce the high-frequency content in the DAC steps. The filtering between the DAC output and the input to the D2S reduces higher-order DAC harmonics from feeding into the internal OPS path when the external input path is selected. Feedthrough between the internal and external OPS paths increases with increasing frequency; however, the input filter rolls off the DAC harmonics before the harmonics couple to VOUT (pin 10) through the deselected OPS signal path. Figure 96 shows an example of a doubly-terminated differential filter from the DAC to the THS3217 D2S inputs at pins 2 and 3.The DAC is modeled as two, fixed, 10-mA currents and a differential, ac-current source. The 10-mA dc midscale currents set up the average common-mode voltage at the DAC outputs and D2S inputs at 10 mA × 25 Ω = 0.25 V_CM. The total voltage swing on the DAC outputs is 0 V to 0.5 V.

Figure 96. 200-MHz Butterworth Filter Between DAC and D2S Inputs

Some of the guidelines to consider in this filter design are:

1. The filter cutoff is adjusted to hit a standard value in the standard high-frequency, chip inductors kits.
2. The required filter output capacitance is reduced from the design value of 14.4 pF to 12 pF to account for the D2S input capacitance of 2.4 pF, as reported in the D2S Electrical Characteristics table.
3. The capacitor at the DAC output pins must also be reduced by the expected DAC output pin capacitance. The DAC output capacitance is often specified as 5 pF, but is usually much lower. Contact the DAC manufacturer for an accurate value.

Figure 97 shows the TINA-simulated filter response for the input-stage filter. The low-frequency 34-dBΩ gain is due to the 50-Ω differential resistance at the DAC output terminals. At 400 MHz, this filter is down 16 dB from the 50-Ω level; it is also very flat through 100 MHz.

Figure 97. Simulated, Differential-Input Filter Response

In the example design of Figure 95, a 100-MHz, third-order Bessel filter is placed between the D2S output and the external OPS input. Another 50-MHz, third-order Bessel filter is placed at the input of a very-high, output-swing THS3091 stage. A double-pole, double-throw (DPDT) relay selects the THS3091 path when the internal OPS path is selected in the THS3217. Figure 95 shows this design. The key operational considerations in this design include:

1. When the external OPS path is selected, the 2-V_PP maximum D2S output swing experiences a 1.1-dB insertion loss from the interstage filter between VO1 (pin 6) and VIN+ (pin 9). A standard value inductor is used and the 255-Ω termination accounts for the internal 18.5-kΩ element. The 10-Ω resistor at pin 9 isolates the OPS input from the 52-pF filter capacitor. To recover the insertion loss and produce a maximum 5-V_PP output, the OPS gain is set to 2.84 V/V. When the interstage filter path is selected, the two DPDT relays pass the OPS output on directly from the 49.9-Ω output matching resistor to V_O, and the THS3091 can be disabled to conserve power.
2. To deliver 20 V_PP at the V_O output, select the THS3091 path. Select the internal OPS path to bypass the 100-MHz filter (1.1-dB insertion loss) in order to give a maximum 5.7-V_PP output at VOUT (pin 11). The two DPDT relays switch position, and the 49.9 Ω at the OPS output becomes part of the 50-MHz, third-order Bessel filter into the THS3091 stage. This filter has a 2-dB insertion loss requiring a gain of 4.4 V/V in the THS3091 to deliver 20 V_PP from the OPS output.
3. Figure 98 and Figure 99 show the frequency response and harmonic distortion performance of the dual output-voltage system. The frequency response is normalized to 0 dB to make bandwidth comparisons easier.

10.1.1.1.3 Application Curves

Figure 98. Frequency Response of the 5-V_PP and 20-V_PP Channels

Figure 99. Harmonic Distortion Performance of the 5-V_PP and 20-V_PP Channels

10.1.1.2.1 Design Requirements

To design a high-voltage, high-speed pulse generator with minimum overshoot, use the parameters listed in Table 8 as the input parameters.

10.1.1.2.2 Detailed Design Procedure

Figure 100 shows an example design using the THS3217 to deliver a 10-V_PP maximum voltage from a DAC input, and includes an example external, third-order, interstage Bessel filter. Some of the salient considerations for this design include:

1. Reduced DAC output current with increased termination. This example is intended to be used with a current-sourcing DAC with an output compliance voltage of at least 1 V on a 0.5-V common-mode voltage. The 10-mA, single-ended, DAC tail current produces a 0-V to 1-V swing on each 100-Ω termination. The resulting 2-V_PP differential DAC signal produces a higher SNR signal at the THS3217 inputs.
2. The midscale buffer is not used. The VREF pin is grounded to set the inputs to a 4-V_PP ground-centered maximum output swing at VO1 (pin 6). The external input to the OPS is selected by setting PATHSEL to 3.3 V (anything over 1.3 V is adequate, or tie this pin to +V_CC for fixed, external-path operation).
3. The interstage Bessel filter is –0.3-dB flat through 20 MHz, with only 1.6 dB of insertion loss. The filter is designed to be low insertion-loss with relatively high resistor values. The filter uses standard inductor values. The capacitors are also standard-value, and slightly off from the exact filter solution. The final resistor to ground is designed for 500 Ω, but increased here to a standard 511 Ω externally to account for the internal 18.5-kΩ resistor on the external OPS input pin to GND. To isolate the last 47-pF filter capacitor from the OPS input stage, a 10-Ω series resistor is added close to the pin 9 input.
4. The filter adds 1.6 dB of insertion loss that is recovered, to achieve a 10-V_PP maximum output by designing the OPS for a gain of 3 V/V. Looking at Table 7, this gain setting requires the 232-Ω external R_F and 113-Ω R_G to ground for best operation.
5. For 10-V_PP maximum output, using the ±7.5-V supplies shown here gives adequate headroom in the OPS output stage. The operating maximum supply of 15.8 V requires a 5% tolerance on these ±7.5-V supplies.
6. The Bessel filter gives a very low overshoot full-scale output step-response, as shown in the 10-MHz, ±5-V square wave of Figure 102. The frequency response of the system is shown in Figure 101.

10.1.1.2.3 Application Curves

Figure 101. Frequency Response of the System With the Interstage Bessel Filter

Figure 102. Pulse Response of the System With the Interstage Bessel Filter

10.1.1.3.1 Design Requirements

The very-high peak output current and slew rate of the THS3217 OPS make it particularly suitable for driving heavy capacitive loads, such as the piezo elements used in continuous wave (CW) applications that require high-amplitude, sinusoidal-type excitations. The driver is quickly disabled during the receive time when the output TR switch is moved to receive mode. Figure 103 shows an example design using the internal midscale buffer to bias all the stages to midsupply on a single 15-V design. There are many elements to this example that also apply to any single-supply application. The key points here are:

1. The differential DAC input signal is ac-coupled to the D2S input, and the termination resistors are scaled up and biased to midsupply using the output of the midscale buffer, VMID_OUT (pin 15). The 10-nF blocking capacitors before the 1.62 kΩ termination resistors set the high-pass pole at 10 kHz.
2. The internal divider resistors of the midscale buffer are decoupled using a 1-µF capacitor on VMID_IN (pin 1). Use of the capacitor improves both noise and PSRR through the reference buffer stage. In turn, the noise injected by the bias source is reduced at the various places the buffer output is used.
3. V_{MID_OUT} is also applied to the VREF input (pin 14) to hold the D2S output centered on the single 15-V supply. There is minimal dc current into VREF (pin 14) because the D2S input buffers operate at the same common-mode voltage, V_{MID_OUT}.
4. The D2S output is dc biased at midsupply and delivers two times the differential swing applied at its inputs. Assuming 2 V_PP at the D2S inputs implies 4 V_PP at the D2S output pins. Lower input swings are supported with the gain in the OPS adjusted to meet the desired output maximum.
5. The filter in Figure 103 is a 0.2-dB ripple, second-order Chebyshev filter at 15 MHz. If the desired maximum frequency is 12 MHz, for instance, this filter is attenuating the HD2 and HD3 out of the D2S by approximately 3 dB and 5 dB, respectively. Increased attenuation can be provided with higher-order filters, but this simple filter does a good job of band-limiting the high-frequency noise from the D2S outputs before the noise gets into the OPS stage.
6. The dc bias voltage at VO1 drives a small dc current into the 18.5-kΩ resistor to ground at the OPS external input, VIN+ (pin 9). The error voltage due to the bias current will level-shift the dc voltage at the OPS noninverting input through the 105-Ω filter resistor. This offset will be amplified by the OPS gain since its R_G element is referenced to the V_MID output with a dc gain of 3.4 V/V.
7. The logic lines are still referenced to ground in this single-supply application. The external path to the OPS is selected by connecting PATHSEL (pin 4) to +V_CC. DISABLE (pin 10) is grounded in this example in order to hold the OPS on. If the disable feature is required by the application, drive the OPS using a standard logic control driver. Note that the midscale buffer output still drives R_G and R_F to midsupply in this configuration with the OPS disabled.
8. The R_G element can be ac coupled to ground through a capacitor to operate at midsupply. Figure 103 shows the midscale buffer driving R_G, thus eliminating the need for an added capacitor. Using a blocking capacitor moves the dc gain to 1 V/V. The voltage on the external, noninverting input of the OPS sets the dc operating point. Use of a blocking capacitor also lightens the load on the midscale buffer output, and eliminates the bias on R_G when the OPS is disabled.
9. Piezo element drivers operate in a relatively low-frequency range; therefore, the OPS R_F is scaled up even further than the values suggested in Table 7. An increased R_F allows R_G to also be scaled up, thereby reducing the load on the midscale buffer, and allow a lower series output resistor to be used into the 300-pF capacitive load.
10. The peak charging current into the capacitive load occurs at the peak dV/dT point. Assuming a 12-MHz sinusoid at 12 V_PP requires a peak output current from the OPS of 6 V_PEAK × 2π × 12 MHz × 300 pF = 135 mA. This result matches the rated minimum peak output current of the OPS.

Using a very low series resistor limits the waveform distortion due to the I × R drop at the peak charging point around the sinusoidal zero crossing. The 135 mA through 3.3 Ω causes a 0.45-V peak drop to the load capacitance around zero crossing. The voltage drop across the series output resistor increases the apparent third harmonic distortion at the capacitive load. Figure 45 and Figure 46 show 10-V_PP distortion sweeps into various capacitor loads. The results shown in these figures are for the OPS only because the results set the harmonic distortion performance in this example.

10.1.1.4.1 Design Requirements

An easy way to insert a dc offset into the signal channel (without sacrificing any of the DAC dynamic range) is to apply the desired offset at VMID_IN and use it to bias VREF (pin 14) and VIN+ (pin 9). An example is shown in Figure 104. This example shows a relatively low maximum differential input of 1 V_PP on any compliance voltage required by the DAC. Other configuration options include:

1. The D2S output is offset using a dc input at VMID_IN (pin 1). Although shown here as ±2 V, the dc offset expands to ±3.5 V when using ±7.5-V supplies.
2. Connecting VMID_OUT to the VREF input places the D2S output at the dc offset voltage along with a gain of 2 V/V version of the differential input voltage. The stated range of ±2 V, along with the ±0.5 V out of the upper input buffer, requires a peak output current from VMID_OUT of 2.5 V / 150 Ω = 16.7 mA. This value is well below the rated minimum linear output current of 40 mA.
3. The dc offset voltage is then applied to the external OPS input. Connecting the circuit in this manner results in no additional dc gain between the D2S and OPS outputs, while it continues to retain the signal gain of the OPS configured as an inverting amplifier. The values of R_F and R_G in this application example are derived from Table 4. The OPS is setup for a gain of –4 V/V in this example. Using the resistor values from Table 4 results in the widest bandwidth for the OPS; however, the R_G = 54.9 Ω resistor presents a heavy load to the D2S output. In such cases, scaling up the resistors in the OPS helps reduce the loading on the D2S output at the expense of reduced OPS bandwidth.
4. No filtering is shown in this example; however, introducing filtering in the OPS R_G path is certainly possible. In such cases, the R_G element is also the filter termination resistor. Any filtering adds some insertion loss that can be recovered in the OPS stage.

10.1.1.5.1 Design Requirements

Certain applications require the differential DAC output voltage to be level-translated from one common-mode (compliance) level to a differential output at a different common-mode level. The THS3217 performs this function directly using the very flexible blocks provided internally. Figure 105 shows an example of such an application, where the differential gain is always 4 V/V. The differential gain is fine-tuned down by setting the insertion loss in the differential post-filter. The considerations critical to this application include:

1. The input is dc-coupled with the appropriate termination impedance required by the DAC. Use a high-frequency, antialiasing filter at the input to limit DAC feedthrough in the deselected OPS internal input.
2. The output common-mode control is set with the voltage applied to the VMID buffer input at VMID_IN (pin 1). The circuit is configured so that the output at VMID_OUT (pin 15) drives both VREF (pin 14), in order to set the D2S dc output voltage, and VIN+ (pin 9).
3. The D2S output available at VO1 (pin 6) provides one side of the differential-output, and is dc-biased at V_{MID_OUT}. This VO1 also drives the R_G resistor for the OPS in an inverting gain of –1 V/V. The dc bias level at the R_G input and the V+ input of the OPS are the same voltage; therefore, no level shift through the OPS occurs. The OPS outputs an inverted version of the D2S output signal at the same common-mode voltage (V_{MID_OUT}). The wideband, differential signal with independent output common-mode voltage control can now be applied to a differential filter and on to the next stage.
4. Make sure that the differential filter only has differential resistors and capacitors. Termination resistors to ground level shift the input common-mode voltage, while differential resistors transfers the desired V_{MID_OUT} directly through the filter.
5. If the desired V_{MID_OUT} + differential signal combined clips in the OPS or D2S stages, offset the supplies to gain headroom. For instance, if a 5-V output common-mode voltage is required with a 10-V_PP differential signal, the OPS and D2S must deliver 2.5-V to 7.5-V output swings. The D2S has the higher headroom requirement at 1.55 V (max). Operating the THS3217 with –5 V and +10 V supplies stays within the rated maximum of 15.8 V total supply range, and provide adequate headroom for the positive offset swing requirement. Note that the logic lines are still referenced to GND by pin 7. Tying PATHSEL (pin 4) to +V_CC holds this design in the external path mode required.