In some cases, a characteristic curve can only be generated through simulation. A good example of this scenario is the output balance plot of Figure 7-40. This plot shows the best-case output balance (output differential signal versus output common-mode signal) using exact matching on the external resistors in simulation using a single-ended input to differential output configuration. The actual output balance is set by resistor mismatch at low frequencies but intersects and follows the high-frequency portion of Figure 7-40.

The remaining simulated plots include:

• A_OL gain and phase, see Figure 7-37.
• Large- and small-signal settling times, see Figure 7-11 and Figure 7-29.
• Closed-loop output impedance versus frequency, see Figure 7-38.
• CMRR vs frequency, see Figure 7-41.
• PSRR vs frequency and output common-mode voltage, see Figure 7-42, Figure 7-47, and Figure 7-48.