米6体育平台手机版

ZHCSQ68A May 2022 – December 2022 TLIN1431-Q1

PRODUCTION DATA

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

RGY|20

散热焊盘机械数据 (封装 | 引脚)

订购信息

zhcsq68a_oa

6.8 AC Switching Characteristics

parameters valid over –40℃ ≤ T_J ≤ 150 ℃ range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
Device Switching Characteristics
t_{rx_pdr} t_{rx_pdf}	Receiver rising/falling propagation delay time (ISO/DIS 17987 Param 31)	R_RXD = 2.4 kΩ, C_RXD = 20 pF (See Figure 7-3, Figure 7-4)			6	µs
t_{rs_sym}	Symmetry of receiver propagation delay time Receiver rising propagation delay time (ISO/DIS 17987 Param 32)	Rising edge with respect to falling edge, (t_{rx_sym} = t_{rx_pdf} – t_{rx_pdr}), R_RXD = 2.4 kΩ, C_RXD = 20 pF (See Figure 7-3, Figure 7-4)	–2		2	µs
t_LINBUS	LIN wakeup time (minimum dominant time on LIN bus for wakeup)	See Figure 7-6, Figure 8-11 and Figure 8-12	25	100	150	µs
t_CLEAR	Time to clear false wakeup prevention logic if LIN bus had a bus stuck dominant fault (recessive time on LIN bus to clear bus stuck dominant fault)	See Figure 8-12	10		60	µs
t_{TXD_DTO}	Dominant state time out		20	45	80	ms
t_EN	Enable pin deglitch time	Time enable pin state change before initiating mode change or sampling TXD pin	3		12	µs
t_{MODE_CHANGE}	Mode change delay time	Time to change from normal mode to sleep mode through EN pin: See Figure 7-5			100	µs
t_DETECT	Time to detect Pin vs SPI and I/O voltage level at power up⁽¹⁾	Time from coming out of UV_CC and device determines these states			2	µs
t_{DET_INH}	Time to detect which output INH or WKRQ at power up	Time from coming out of UV_CC and device determines these states			25	µs
t_NOMINIT	Normal mode initialization time	Time for normal mode to initialize and data on RXD pin to be valid, includes t_{MODE_CHANGE} for standby mode to normal mode See Figure 7-5			45	µs
t_{RSTN_act}	Time required for V_CC ≥ UV_CC to leave Restart mode	V_CC ≥ UV_CC	1.5	2	2.5	ms
t_nRSTIN	Input pulse required on the nRST pin to recognize a device reset.		120			µs
t_{NRST_TOG}	nRST pin output toggle high to low to high time	reg 29h[5] = 0 (Default value in SPI control. Value in pin control except for watchdog failure.)	1.5	2	2.5	ms
t_{NRST_TOG}	nRST pin output toggle high to low to high time	reg 29h[5] = 1 (Value in pin control for watchdog failure.)	10	15	20	ms
t_INITWD	Initial long watchdog window time required to trigger first watchdog input trigger when entering Standby mode or Normal mode	WDI input trigger or SPI write command	150		200	ms
t_{INACT_FS}	Timer for inactivity coming out of sleep mode and when coming out of failsafe mode to determine if caused event has been cleared ⁽¹⁾	Default values and can be programmed to different values in SPI control.	4	5	6	min
t_PWRUP	Time from V_SUP exceedingUV_SUP until INH active	V_CC > UV_CC, INH = V_SUP, V_CC load of 50 mA @ 22 µF capacitance			3	ms
t_PWRUP	Time from V_SUP exceedingUV_{SUP and}V_CC exceeding UV_CC until WKRQ active	V_CC > UV_CC, WKRQ = V_CC, V_CC load of 50 mA @ 22 µF capacitance			3	ms
t_TOGGLE	RXD pulse width when waking from sleep mode	register 'h12[2] = 1	5		15	µs
t_UVFLTR	Undervoltage detection delay time for V_CC		3		4	ms
t_VSC	Short to ground on VCC detection delay time		75	100	130	µs
t_LDOON	Time LDO is on to determine if a short circuit event is present after a previous uncleared detection		2		3	ms
t_{MODE_STBY_NOM}	Standby to normal mode change time based upon SPI write				70	µs
t_{MODE_NOM_SLP}	SPI write to go to sleep from normal	Time from SPI sleep command where LIN transceiver is off and RXD doesn't reflect the LIN bus			200	µs
t_{MODE_NOM_STBY}	SPI write to go to standby from normal mode				70	µs
t_{WKRQ_SLP}	Time WKRQ turns on after a wake event when device is in sleep mode	Dependent upon LDO turning on and ramp time. Time provided is based upon 1 µs ramp and LDO being at 2 V.	450			µs
t_{INH_SLP}	Time INH turns on after a wake event when device is in sleep mode				210	µs
t_{INH_NOM_SLP}	SPI write to go to sleep from normal mode and INH turns off				70	µs
t_{WK_WIDTH_MIN}	Minimum WAKE pin pulse width (SPI mode only) ⁽²⁾ ⁽³⁾ ⁽⁴⁾	Minimum WAKE Pin pulse width Register 8'h11[3:2] = 00b; See Figure 8-46	10			ms
		Minimum WAKE Pin pulse width Register 8'h11[3:2] = 01b; See Figure 8-46	20			ms
		Minimum WAKE Pin pulse width Register 8'h11[3:2] = 10b; See Figure 8-46	40			ms
		Minimum WAKE Pin pulse width Register 8'h11[3:2] = 11b; See Figure 8-46	80			ms
t_{WK_WIDTH_INVALID}	Maximum Pulse width that is considered invalid (SPI mode only) ⁽²⁾ ⁽³⁾	Maximum WAKE Pin pulse width that is considered invalid Register 8'h11[3:2] = 00b; See Figure 8-46			5	ms
		Maximum WAKE Pin pulse width that is considered invalid Register 8'h113:2] = 01b; See Figure 8-46			10	ms
		Maximum WAKE Pin pulse width that is considered invalid Register 8'h11[3:2] = 10b; See Figure 8-46			20	ms
		Maximum WAKE Pin pulse width that is considered invalid Register 8'h11[3:2] = 11b; See Figure 8-46			40	ms
t_{WK_WIDTH_MAX}	Maximum WAKE pin pulse width to be considered valid (SPI mode only) ⁽²⁾	Maximum WAKE Pin pulse window Register 8'h11[1:0] = 00b; See Figure 8-46	750		950	ms
		Maximum WAKE Pin pulse window Register 8'h11[1:0] = 01b; See Figure 8-46	1000		1250	ms
		Maximum WAKE Pin pulse window Register 8'h11[1:0] = 10b; See Figure 8-46	1500		1875	ms
		Maximum WAKE Pin pulse window Register 8'h11[1:0] = 11b; See Figure 8-46	2000		2500	ms
t_{WK_CYC}	Sampling window for cyclic sensing wake; Standby or Sleep mode; see Figure 8-49	Register 8'h12[5] = 0	10	30	40	µs
t_{WK_CYC}		Register 8'h12[5] = 1	60	75	90	µs
Fast Mode
DR	Data Rate	5.5 V ≤ V_SUP ≤ 18 V, R_LIN = 500 Ω and C_LIN(bus) = 600 pF			200	kbps
t_{rx_pdr} t_{rx_pdf}	Receiver rising/falling propagation delay time (ISO/DIS 17987 Param 31)	R_RXD = 2.4 kΩ, C_RXD = 20 pF (See Figure 7-3, Figure 7-4			5	µs
t_txr/f	LIN transmitter rise and fall time	5.5 V ≤ V_SUP ≤ 18 V, R_LIN = 500 Ω and C_LIN(bus) = 600 pF, 80%/20%			1.5	µs
t_{FM_CHANGE}	Fast mode determination time for entering or leaving	Based upon EN and TXD voltage levels	70	90	110	µs
t_FMTXD	TXD pin pulse width to enter fast mode	Pulse must start after t_EN and finish before t_{FM_CHANGE}	5		25	µs
SPI Switching Characteristics
f_SCK	SCK, SPI clock frequency ⁽¹⁾				4	MHz
t_SCK	SCK, SPI clock period ⁽¹⁾	See Figure 7-7	250			ns
t_RSCK	SCK rise time ⁽¹⁾	See Figure 7-7			40	ns
t_FSCK	SCK fall time ⁽¹⁾	See Figure 7-7			40	ns
t_SCKH	SCK, SPI clock high ⁽¹⁾	See Figure 7-7	125			ns
t_SCKL	SCK, SPI clock low ⁽¹⁾	See Figure 7-7	125			ns
t_ACC	First read access time from chip select ⁽¹⁾	See Figure 7-7	50			ns
t_CSS	Chip select setup time ⁽¹⁾	See Figure 7-7	100			ns
t_CSH	Chip select hold time ⁽¹⁾	See Figure 7-7	100			ns
t_CSD	Chip select disable time ⁽¹⁾	See Figure 7-7	50			ns
t_SISU	Data in setup time ⁽¹⁾	See Figure 7-7	50			ns
t_SIH	Data in hold time ⁽¹⁾	See Figure 7-7	50			ns
t_SOV	Data out valid ⁽¹⁾	See Figure 7-7			80	ns
t_RSO	SO rise time ⁽¹⁾	See Figure 7-7			40	ns
t_FSO	SO fall time ⁽¹⁾	See Figure 7-7			40	ns

(1) Specified by design

(2) This parameter is valid only when register 11h[7:6] = 11b

(3) This is the minimum pulse width for a WAKE pin input that device will detect as a good pulse. Values between the min t_{WK_WIDTH_MIN}
and max t_{WK_WIDTH_INVALID}is indeterminant and may or may not be considered valid.

(4) This parameter is set based upon the programmed value for t_{WK_WIDTH_INVALID} register 11h[3:2]