SLVS568D January   2005  – April 2016 TLV341 , TLV341A , TLV342 , TLV342S

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information: TLV341
    5. 6.5  Thermal Information: TLV342
    6. 6.6  Thermal Information: TLV342S
    7. 6.7  Electrical Characteristics: V+ = 1.8 V
    8. 6.8  Electrical Characteristics: V+ = 5 V
    9. 6.9  Shutdown Characteristics: V+ = 1.8 V
    10. 6.10 Shutdown Characteristics: V+ = 5 V
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PMOS Input Stage
      2. 7.3.2 CMOS Output Stage
      3. 7.3.3 Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resource
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
V+ Supply voltage(2) –0.3 5.5 V
VID Differential input voltage(3) ±5.5 V
VI Input voltage (either input or shutdown) –0.3 5.5 V
VO Output voltage –0.3 VCC + 0.3 V
TJ Operating virtual-junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values (except differential voltages) are with respect to the network GND.
(3) Differential voltages are at IN+ with respect to IN−.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
V+ Supply voltage (single-supply operation) 1.5 5.5 V
TA Operating free-air temperature –40 125 °C

6.4 Thermal Information: TLV341

THERMAL METRIC(1) TLV341 UNIT
DBV
(SOT-23)		 DCK
(SC70)		 DRL
(SOT)
6 PINS 6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 193.4 196.8 221.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 145.6 82.4 109.1 °C/W
RθJB Junction-to-board thermal resistance 44.1 95.2 111.4 °C/W
ψJT Junction-to-top characterization parameter 34.1 1.8 6.2 °C/W
ψJB Junction-to-board characterization parameter 43.4 93.2 109.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Thermal Information: TLV342

THERMAL METRIC(1) TLV342 UNIT
D
(SOIC)		 DGK
(MSOP)		 RUG
(X2QFN)
8 PINS 8 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 123.6 192.3 167 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 69.8 78.2 56.5 °C/W
RθJB Junction-to-board thermal resistance 63.9 112.6 94.3 °C/W
ψJT Junction-to-top characterization parameter 24.4 15.2 4.1 °C/W
ψJB Junction-to-board characterization parameter 63.4 111.2 94 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.6 Thermal Information: TLV342S

THERMAL METRIC(1) TLV342S UNIT
RUG
(X2QFN)
10 PINS
RθJA Junction-to-ambient thermal resistance 158.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.6 °C/W
RθJB Junction-to-board thermal resistance 87.9 °C/W
ψJT Junction-to-top characterization parameter 1 °C/W
ψJB Junction-to-board characterization parameter 87 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.7 Electrical Characteristics: V+ = 1.8 V

V+ = 1.8 V, GND = 0 V, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted). See Shutdown Characteristics: V+ = 1.8 V.
PARAMETER TEST CONDITIONS TA MIN TYP(1) MAX UNIT
VIO Input offset voltage Standard grade 25°C 0.3 4 mV
Full range 4.5
A grade 25°C 0.3 1.25
0°C to 125°C 0.3 1.5
–40°C to 125°C 0.3 1.7
αVIO Average temperature coefficient of input offset voltage Full range 1.9 μV/°C
IIB Input bias current 25°C 1 100 pA
–40°C to 85°C 375
–40°C to 125°C 3000
IIO Input offset current 25°C 6.6 fA
CMRR Common-mode rejection ratio 0 ≤ VICR ≤ 1.2 V 25°C 60 85 dB
Full range 50
kSVR Supply-voltage rejection ratio 1.8 V ≤ V+ ≤ 5 V 25°C 75 95 dB
Full range 65
VICR Common-mode input voltage range CMRR ≥ 60 dB 25°C 0 1.2 V
AV Large-signal voltage gain(2) RL = 10 kΩ to 1.35 V 25°C 70 110 dB
Full range 60
RL = 2 kΩ to 1.35 V 25°C 65 100
Full range 55
VO Output swing
(delta from supply rails)		 RL = 2 kΩ to 1.35 V Low level 25°C 22 50 mV
Full range 75
High level 25°C 25 50
Full range 75
RL = 10 kΩ to 1.35 V Low level 25°C 14 20
Full range 25
High level 25°C 7 20
Full range 25
ICC Supply current (per channel) 25°C 70 150 μA
Full range 200
IOS Output short-circuit current Sourcing 25°C 6 12 mA
Sinking 10 20
SR Slew rate RL = 10 kΩ(3) 25°C 0.9 V/μs
GBW Unity-gain bandwidth RL = 10 kΩ, CL = 200 pF 25°C 2.2 MHz
φm Phase margin RL = 100 kΩ, CL = 200 pF 25°C 55 °
Gm Gain margin RL = 100 kΩ, CL = 200 pF 25°C 15 dB
Vn Equivalent input noise voltage f = 1 kHz 25°C 33 nV/√Hz
In Equivalent input noise current f = 1 kHz 25°C 0.001 pA/√Hz
THD Total harmonic distortion f = 1 kHz, AV = 1, RL = 600 Ω,
VI = 1 VPP 		25°C 0.015%
(1) Typical values represent the most likely parametric norm.
(2) GND + 0.2 V ≤ VO ≤ V+ – 0.2 V
(3) Connected as voltage follower with 2-VPP step input. Number specified is the slower of the positive and negative slew rates.

6.8 Electrical Characteristics: V+ = 5 V

V+ = 5 V, GND = 0 V, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted). See Shutdown Characteristics: V+ = 5 V.
PARAMETER TEST CONDITIONS TA MIN TYP(1) MAX UNIT
VIO Input offset voltage Standard grade 25°C 0.3 4 mV
Full range 4.5
A grade 25°C 0.3 1.25
0°C to 125°C 0.3 1.5
–40°C to 125°C 0.3 1.7
αVIO Average temperature coefficient of input offset voltage Full range 1.9 μV/°C
IIB Input bias current 25°C 1 200 pA
–40°C to 85°C 375
–40°C to 125°C 3000
IIO Input offset current 25°C 6.6 fA
CMRR Common-mode rejection ratio 0 ≤ VICR ≤ 4.4 V 25°C 75 90 dB
Full range 70
kSVR Supply-voltage rejection ratio 1.8 V ≤ V+ ≤ 5 V 25°C 75 95 dB
Full range 65
VICR Common-mode input voltage range CMRR ≥ 70 dB 25°C 0 4.4 V
AV Large-signal voltage gain(2) RL = 10 kΩ to 2.5 V 25°C 80 110 dB
Full range 70
RL = 2 kΩ to 2.5 V 25°C 75 105
Full range 60
VO Output swing
(delta from supply rails)		 RL = 2 kΩ to 2.5 V Low level 25°C 40 60 mV
Full range 85
High level 25°C 25 60
Full range 85
RL = 10 kΩ to 2.5 V Low level 25°C 18 30
Full range 40
High level 25°C 7 15
Full range 20
ICC Supply current (per channel) 25°C 75 150 μA
Full range 200
IOS Output short-circuit current Sourcing 25°C 60 113 mA
Sinking 80 115
SR Slew rate RL = 10 kΩ(3) 25°C 1 V/μs
GBW Unity-gain bandwidth RL = 10 kΩ, CL = 200 pF 25°C 2.3 MHz
φm Phase margin RL = 100 kΩ, CL = 200 pF 25°C 55 °
Gm Gain margin RL = 100 kΩ, CL = 200 pF 25°C 15 dB
Vn Equivalent input noise voltage f = 1 kHz 25°C 33 nV/√Hz
In Equivalent input noise current f = 1 kHz 25°C 0.001 pA/√Hz
THD Total harmonic distortion f = 1 kHz, AV = 1, RL = 600 Ω,
VI = 1 VPP 		25°C 0.012%

6.9 Shutdown Characteristics: V+ = 1.8 V

V+ = 1.8 V, GND = 0 V, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
ICC(SHDN) Supply current in shutdown mode VSD = 0 V 25°C 0.01 1 μA
Full range 1.5
t(on) Amplifier turnon time 25°C 5 μs
VSD Recommended shutdown pin voltage range On mode 25°C 1.5 1.8 V
Shutdown mode 0 0.5

6.10 Shutdown Characteristics: V+ = 5 V

V+ = 5 V, GND = 0 V, VIC = VO = V+/2, RL > 1 MΩ (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
ICC(SHDN) Supply current in shutdown mode VSD = 0 V 25°C 0.01 1 μA
Full range 1.5
t(on) Amplifier turnon time 25°C 5 μs
VSD Recommended shutdown pin voltage range On mode 25°C 4.5 5 V
Shutdown mode 0 0.8

6.11 Typical Characteristics

TLV341 TLV341A TLV342 TLV342S g_icc_vcc_lvs568.gif Figure 1. Supply Current vs
Supply Voltage
TLV341 TLV341A TLV342 TLV342S g_voswing_vcc_rl2k_lvs568.gif Figure 3. Output Voltage Swing vs
Supply Voltage
TLV341 TLV341A TLV342 TLV342S g_isrc_vo_v27_lvs568.gif Figure 5. Source Current vs
Output Voltage
TLV341 TLV341A TLV342 TLV342S g_isnk_vo_v27_lvs568.gif Figure 7. Sink Current vs
Output Voltage
TLV341 TLV341A TLV342 TLV342S g_vio_vcm_v27_lvs568.gif Figure 9. Offset Voltage vs
Common-Mode Voltage
TLV341 TLV341A TLV342 TLV342S g_vi_vo_v25_lvs568.gif Figure 11. Input Voltage vs Output Voltage
TLV341 TLV341A TLV342 TLV342S g_slew_vcc_vi082_lvs568.gif Figure 13. Slew Rate vs
Supply Voltage
TLV341 TLV341A TLV342 TLV342S g_slew_temp_lvs568.gif Figure 15. Slew Rate vs
Temperature
TLV341 TLV341A TLV342 TLV342S g_psrr_freq_lvs568.gif Figure 17. PSRR vs Frequency
TLV341 TLV341A TLV342 TLV342S g_thdn_freq_lvs568.gif Figure 19. Total Harmonic Distortion +Noise
vs Frequency
TLV341 TLV341A TLV342 TLV342S g_freqresp_temp_lvs568.gif Figure 21. Frequency Response vs
Temperature
TLV341 TLV341A TLV342 TLV342S g_freqresp_rl_v5_lvs568.gif Figure 23. Frequency Response vs RL
TLV341 TLV341A TLV342 TLV342S g_sml_noninv_tam40_lvs568.gif Figure 25. Small-Signal Noninverting Response
TLV341 TLV341A TLV342 TLV342S g_sml_noninv_ta25_lvs568.gif Figure 27. Small-Signal Noninverting Response
TLV341 TLV341A TLV342 TLV342S g_sml_noninv_ta125_lvs568.gif Figure 29. Small-Signal Noninverting Response
TLV341 TLV341A TLV342 TLV342S g_sml_inv_tam40_lvs568.gif Figure 31. Small-Signal Noninverting Response
TLV341 TLV341A TLV342 TLV342S g_sml_inv_ta25_lvs568.gif Figure 33. Small-Signal Inverting Response
TLV341 TLV341A TLV342 TLV342S g_sml_inv_ta125_lvs568.gif Figure 35. Small-Signal Inverting Response
TLV341 TLV341A TLV342 TLV342S g_iib_temp_lvs568.gif Figure 2. Input Bias Current vs
Temperature
TLV341 TLV341A TLV342 TLV342S g_voswing_vcc_rl10k_lvs568.gif Figure 4. Output Voltage Swing vs
Supply Voltage
TLV341 TLV341A TLV342 TLV342S g_isrc_vo_v5_lvs568.gif Figure 6. Source Current vs
Output Voltage
TLV341 TLV341A TLV342 TLV342S g_isnk_vo_v5_lvs568.gif Figure 8. Sink Current vs
Output Voltage
TLV341 TLV341A TLV342 TLV342S g_vio_vcm_v5_lvs568.gif Figure 10. Offset Voltage vs
Common-Mode Voltage
TLV341 TLV341A TLV342 TLV342S g_vi_vo_v135_lvs568.gif Figure 12. Input Voltage vs
Output Voltage
TLV341 TLV341A TLV342 TLV342S g_slew_vcc_vi2_lvs568.gif Figure 14. Slew Rate vs
Temperature
TLV341 TLV341A TLV342 TLV342S g_cmrr_freq_lvs568.gif Figure 16. CMRR vs Frequency
TLV341 TLV341A TLV342 TLV342S g_vin_freq_lvs568.gif Figure 18. Input Voltage Noise vs
Frequency
TLV341 TLV341A TLV342 TLV342S g_thdn_vo_lvs568.gif Figure 20. Total Harmonic Distortion +Noise
vs Output Voltage
TLV341 TLV341A TLV342 TLV342S g_freqresp_rl_v27_lvs568.gif Figure 22. Frequency Response vs RL
TLV341 TLV341A TLV342 TLV342S g_freqresp_cl_lvs568.gif Figure 24. Frequency Response vs CL
TLV341 TLV341A TLV342 TLV342S g_lrg_noninv_tam40_lvs568.gif Figure 26. Large-Signal Noninverting Response
TLV341 TLV341A TLV342 TLV342S g_lrg_noninv_ta25_lvs568.gif Figure 28. Large-Signal Noninverting Response
TLV341 TLV341A TLV342 TLV342S g_lrg_noninv_ta125_lvs568.gif Figure 30. Large-Signal Noninverting Response
TLV341 TLV341A TLV342 TLV342S g_lrg_inv_tam40_lvs568.gif Figure 32. Large-Signal Inverting Response
TLV341 TLV341A TLV342 TLV342S g_lrg_inv_ta25_lvs568.gif Figure 34. Large-Signal Inverting Response
TLV341 TLV341A TLV342 TLV342S g_lrg_inv_ta125_lvs568.gif Figure 36. Large-Signal Inverting Response
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