ZHCSMR5 November   2020 TLV6703-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Pin (SENSE)
      2. 8.3.2 Output Pin (OUT)
      3. 8.3.3 Immunity to Input-Pin Voltage Transients
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > UVLO)
      2. 8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)
      3. 8.4.3 Power-On Reset (VDD < V(POR))
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 VPULLUP to a Voltage Other Than VDD
      2. 9.1.2 Monitoring VDD
      3. 9.1.3 Monitoring a Voltage Other Than VDD
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Resistor Divider Selection
        2. 9.2.2.2 Pullup Resistor Selection
        3. 9.2.2.3 Input Supply Capacitor
        4. 9.2.2.4 Sense Capacitor
      3. 9.2.3 Application Curves
    3. 9.3 Dos and Don'ts
  10. 10Power-Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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7.5 Electrical Characteristics

Over the operating temperature range of TJ = –40°C to +125°C, and 1.8 V < VDD < 18 V (unless otherwise noted).
Typical values are at TJ = 25°C and VDD = 5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(POR) Power-on reset voltage (1) VOLmax = 0.2 V, output sink current = 15 µA 0.8 V
VIT+ Positive-going input threshold voltage VDD = 1.8V and 18 V, TJ = 25°C 398 400 402.5 mV
VDD = 1.8V and 18 V, TJ = –40°C to 125°C 396 404
VIT– Negative-going input threshold voltage VDD = 1.8V and 18 V, TJ = 25°C 391.6 394.5 397.5 mV
VDD = 1.8V and 18 V, TJ = –40°C to 125°C 387 400
Vhys Hysteresis voltage (hys = VIT+ – VIT–) 5.5 12 mV
I(SENSE) Input current (at the SENSE pin) VDD = 1.8 V and 18 V, VI = 6.5 V –25 1 25 nA
VOL Low-level output voltage VDD = 1.8 V, output sink current = 3 mA 250 mV
VDD = 5 V, output sink current = 5 mA 250
Ilkg(OD) Open-drain output leakage-current VDD = 1.8 V and 18 V, VO = VDD 300 nA
VDD = 1.8 V, VO = 18 V 300
IDD Supply current VDD = 1.8 V, no load 5.5 11 µA
VDD = 5 V 6 13
VDD = 12 V 6 13
VDD = 18 V 7 13
UVLO Undervoltage lockout (2) VDD falling 1.3 1.7 V
(1) The lowest supply voltage (VDD) at which output is active; tr(VDD) > 15 µs/V. Below V(POR), the output cannot be determined.
(2) When VDD falls below UVLO, OUT is driven low. The output cannot be determined below V(POR).
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