In a typical TLV6703-Q1 application, the output is connected to a GPIO input of the processor (such as a digital signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or application-specific integrated circuit [ASIC]).

The TLV6703-Q1 device provides an open-drain output (OUT). Use a pullup resistor to hold this line high when the output goes to high impedance (not asserted). To connect the output to another device at the correct interface-voltage level, connect a pullup resistor to the proper voltage rail. The TLV6703-Q1 output can be pulled up to 18 V, independent of the device supply voltage.

Table 8-1 and the Section 8.3.1 section describe how the output is asserted or deasserted. See for a Figure 7-1 timing diagram that describes the relationship between threshold voltage and the respective output.