米6体育平台手机版

ZHCSJX8J August 2018 – May 2021 TLV803E , TLV809E , TLV810E

PRODMIX

封装选项

机械数据 (封装 | 引脚)

DPW|5
- MPSS088
DCK|3
- MPDS295F
DBZ|3
- MPDS108G

散热焊盘机械数据 (封装 | 引脚)

DPW|5
- QFND567C

订购信息

7.6 Timing Requirements

over operating range (T_A = –40℃ to 125℃), 1.7 V ≤ V_DD ≤ 6 V, R_pull-up = 10 kΩ to 6 V (Open Drain only), 10 pF load at RESET pin, Overdrive = 10%, unless otherwise noted. Typical values are at 25℃, V_DD = 3.3 V and V_IT–= 2.93 V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_GI	Glitch immunity	5 % Overdrive⁽¹⁾		10		µs
t_{PD_HL}	Propagation delay from VDD falling below V_IT– to RESET	V_DD = (V_IT+ + 30%) to (V_IT– – 10%)		30	50	µs
t_D	Release time or reset timeout period	Reset time delay variant A ⁽²⁾	130	200	270	ms
		Reset time delay variant B ⁽²⁾; R_UP= 100 kΩ, C_L = 100 pF, 30% Overdrive ⁽³⁾		45	90	µs
		Reset time delay variant B ⁽²⁾		40	80	µs
		Reset time delay variant C ⁽²⁾	6.5	10	13.5	ms
		Reset time delay variant D ⁽²⁾	33	50	67	ms
		Reset time delay variant F ⁽²⁾	260	400	540	ms
t_{MR_PW} ⁽⁴⁾	MR pin pulse duration to initiate RESET, RESET			500		ns
t_{MR_RES} ⁽⁴⁾	Propagation delay from MR low to RESET, RESET	V_DD = 4.5 V, V_MR : V_{MR_H}to V_{MR_L}		700		ns
t_{MR_tD} ⁽⁴⁾	Delay from release MR to deasert RESET, RESET	V_DD = 4.5 V, V_MR : V_{MR_L}to V_{MR_H}	t_D__MIN	t_D__TYP	t_D__MAX	ms

(1) Overdrive = [(V_DD/ V_IT–) - 1] × 100%. Refer to section on VDD glitch immunity

(2) Refer to Device nomenclature table. VDD: (V_IT--10%) to (V_IT+ + 10%)

(3) Specified by design

(4) X2SON Package only