ZHCS891G April 2012 – December 2017 TPA3116D2 , TPA3118D2 , TPA3130D2
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Gain Setting and Master and Slave
- 7.3.2 Input Impedance
- 7.3.3 Startup and Shutdown Operation
- 7.3.4 PLIMIT Operation
- 7.3.5 GVDD Supply
- 7.3.6 BSPx AND BSNx Capacitors
- 7.3.7 Differential Inputs
- 7.3.8 Device Protection System
- 7.3.9 DC Detect Protection
- 7.3.10 Short-Circuit Protection and Automatic Recovery Feature
- 7.3.11 Thermal Protection
- 7.3.12 Device Modulation Scheme
- 7.3.13 Efficiency: LC Filter Required with the Traditional Class-D Modulation Scheme
- 7.3.14 Ferrite Bead Filter Considerations
- 7.3.15 When to Use an Output Filter for EMI Suppression
- 7.3.16 AM Avoidance EMI Reduction
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文档支持
- 12机械、封装和可订购信息
8.2 Typical Application
A 2.1 solution, U1 TPA3116D2 in Master mode 400 kHz, BTL, gain if 20 dB, power limit not implemented. U2 in Slave, PBTL mode gain of 20 dB. Inputs are connected for differential inputs.
Figure 37. Schematic