10.1 Layout Guidelines

• The optimum placement is as close to the connector as possible.
  • EMI during an ESD event can couple from the trace being struck to other nearby unprotected traces, resulting in early system failures.
  • The PCB designer must minimize the possibility of EMI coupling by keeping any unprotected traces away from the protected traces, which are between the TVS and the connector.
• Route the protected traces as straight as possible.
• Eliminate any sharp corners on the protected traces between the TVS and the connector by using rounded corners with the largest radii possible.
  • Electric fields tend to build up on corners, increasing EMI coupling.

Use external and internal ground planes and stitch them together with VIAs as close to the GND pin of TPD4E002 as possible. This allows for a low impedance path to ground so that the device can properly dissipate an ESD event.

10.2 Layout Example

Figure 7. TPD4E002 Example Layout