12.1 Layout Guidelines

For best performance, all traces must be as short as possible. To be most effective, the input and output capacitors must be placed close to the device to minimize the effects that parasitic trace inductances may have on normal operation. Using wide traces for VIN, VOUT, and GND helps minimize the parasitic electrical effects along with minimizing the case to ambient thermal impedance. The CT trace must be as short as possible to reduce parasitic capacitance.

12.2 Layout Example

Figure 34. Layout Recommendation

12.3 Thermal Considerations

The maximum IC junction temperature must be restricted to 125°C under normal operating conditions. To calculate the maximum allowable dissipation, P_D(max) , for a given ambient temperature, use Equation 5 as a guideline.

Equation 5.

where

• P_D(max) is the maximum allowable power dissipation
• T_J(max) is the maximum allowable junction temperature (125°C for the TPS22975)
• T_A is the ambient temperature of the device
• Θ_JA is the junction to air thermal impedance. See the Thermal Information section. This parameter is highly dependent upon board layout.

In Figure 34, notice that the thermal vias are located under the exposed thermal pad of the device. This allows for thermal diffusion away from the device.