ZHCSBP7C October   2013  – December 2018 TPS24750 , TPS24751

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      应用原理图 (12V/10A)
      2.      瞬态输出短路响应
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Descriptions
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  DRAIN
      2. 9.3.2  EN
      3. 9.3.3  FLTb
      4. 9.3.4  GATE
      5. 9.3.5  GND
      6. 9.3.6  IMON
      7. 9.3.7  OUT
      8. 9.3.8  OV
      9. 9.3.9  PGb
      10. 9.3.10 PROG
      11. 9.3.11 SENSE
      12. 9.3.12 TIMER
      13. 9.3.13 VCC
    4. 9.4 Device Functional Modes
      1. 9.4.1 Board Plug-In
      2. 9.4.2 Inrush Operation
      3. 9.4.3 Action of the Constant-Power Engine
      4. 9.4.4 Circuit Breaker and Fast Trip
      5. 9.4.5 Automatic Restart
      6. 9.4.6 Start-Up with Short on Output
      7. 9.4.7 PGb, FLTb, and Timer Operations
        1. 9.4.7.1 Overtemperature Shutdown
        2. 9.4.7.2 Start-Up of Hot-Swap Circuit by VCC or EN
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Power-Limited Start-Up
          1. 10.2.2.1.1 STEP 1. Choose RSENSE, RSET, and RIMON
          2. 10.2.2.1.2 STEP 2. Choose Power-Limit Value, PLIM, and RPROG
          3. 10.2.2.1.3 STEP 3. Choose Output Voltage Rising Time, tON, and Timing Capacitor CT
          4. 10.2.2.1.4 STEP 4. Calculate the Retry-Mode Duty Ratio
          5. 10.2.2.1.5 STEP 5. Select R1, R2, and R3 for UV and OV
          6. 10.2.2.1.6 STEP 6. Choose R4, R5, and C1
        2. 10.2.2.2 Alternative Design Example: Gate Capacitor (dv/dt) Control in Inrush Mode
        3. 10.2.2.3 Additional Design Considerations
          1. 10.2.2.3.1 Use of PGb
          2. 10.2.2.3.2 Output Clamp Diode
          3. 10.2.2.3.3 Gate Clamp Diode
          4. 10.2.2.3.4 Bypass Capacitors
          5. 10.2.2.3.5 Output Short-Circuit Measurements
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
  11. 11Power Supply Recommendations
    1. 11.1 Transient Thermal Impedance
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
      1. 13.1.1 相关文档
    2. 13.2 相关链接
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 Export Control Notice
    8. 13.8 术语表
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.3.9 PGb

This active low, open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PGb pulls low after the drain-to-source voltage of the internal FET has fallen below 150 mV and a 3.4 ms deglitch delay has elapsed. It goes open drain when VDS exceeds 220 mV. PGb assumes high impedance status after a 3.4 ms deglitch delay once VDS of internal FET rises up, resulting from GATE being pulled to GND at the following conditions:

  • An overload current fault occurs (VIMON > 675 mV) and the fault timer times out.
  • A hard output short circuit occurs, leading to V(VCC – SENSE) greater than 60 mV, that is, the fast-trip shutdown threshold has been exceeded.
  • VEN is below its falling threshold.
  • VVCC drops below the UVLO threshold.
  • VOV is above its rising threshold.
  • Die temperature exceeds the OTSD threshold.

This pin can be left floating when not used.
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