10.2.2.1.3 STEP 3. Choose Output Voltage Rising Time, t_ON, and Timing Capacitor C_T

The maximum output voltage rise time, t_ON, set by timer capacitor C_T must suffice to fully charge the load capacitance C_OUT without triggering the fault circuitry. Equation 9 defines t_ON for two possible inrush cases. Assuming that only the load capacitance draws current during startup,

Equation 9.

The next step is to determine the minimum fault-timer period. In Equation 9, the output rise time is t_ON. This is the amount of time it takes to charge the output capacitor up to the final output voltage. However, the fault timer uses the difference between the input voltage and the gate voltage to determine if the TPS2475x is still in inrush limit. The fault timer continues to run until V_GS rises 5.8 V (for V_VCC = 12 V) above the input voltage. Some additional time must be added to the charge time to account for this additional gate voltage rise. The minimum fault time can be calculated using Equation 10.

Equation 10.

where Q_GINT is the Gate charge of the internal FET to reach the 5.8 V gate voltage (see Figure 25), Q_GBLK is the Gate charge of blocking FET (for this design, it is considered that CSD17501Q5A SLPS303 blocking FET is used, take this as '0' if blocking FET is not used) and I_GATE is the minimum gate sourcing current of the TPS2475x, or 20 μA. Overall, Equation 10 leads to a minimum fault time of 4.184 ms. Considering the tolerances of C_OUT, C_T, I_LIM , I_TIMER and P_LIM, the fault timer must be set to a value ≥ 1.4 times of t_FLT obtained, to avoid turning off during start-up, but need to be lower than any maximum fault time limit determined by the device SOA curve (see Figure 27).

For this example, we select 6.3 ms (1.5 x T_FLT) to allow for variation of system parameters such as temperature, load, component tolerance, and input voltage. As per SOA curve (T_A = 25^oC), for approximately 6.5 ms, the power handled by the device is approximately 70 W at 12 V (value obtained from extrapolation). This need to be scaled (derated) by a factor of (150 –T_JDCMAX))/(150 – T_A), where T_JDCMAX is the maximum steady state junction temperature (T_JDMAX = T_A(MAX) + I_LIM² × R_(DS)ON × R_θJA). The scaled power is approximately 34 W. So the power limit of 21 W considered has safe margin of 38% over the derated SOA. This can be depicted through the Figure 42. Also, from Figure 42, from the blue dotted line shown, it can be analyzed that the device at T_A = 25^oC, can tolerate 12 V and 10 A for approximately time 1 ms and can take power of 21 W for duration of approximately 70 to 75 ms.

The timing capacitor is calculated in Equation 11 as 46.67 nF. Selecting the next-highest standard value, 47 nF, yields a 6.35 ms fault time.

Equation 11.

Figure 42. Design Example SOA