10.2.2.2 Alternative Design Example: Gate Capacitor (dv/dt) Control in Inrush Mode

The TPS2475x can be used in applications that expect a constant inrush current. This current is controlled by a capacitor connected from the GATE terminal to GND. A resistor of 1 kΩ placed in series with this capacitor prevents it from slowing a fast-turnoff event. In this mode of operation, the internal FET operates as a source follower, and the slew rate of the output voltage approximately equals the slew rate of the gate voltage (see Figure 43).

To implement a constant-inrush-current circuit, choose the time to charge, ∆t, using Equation 14.

Equation 14.

where C_OUT is the output capacitance, V_VCC is the input voltage, and I_CHG is the desired charge current. Choose I_CHG < P_LIM / V_VCC to prevent power limiting from affecting the desired current.

To select the gate capacitance use Equation 15. where, I_GATE is the nominal gate current and C_INTRS, the effective capacitance contributed by the internal FET (approximately 175 pF). In addition, the effect of other capacitances like the capacitance offered by the usage of the Blocking FET (C_BLK) and other component capacitances C_PR (due to external gate protection diodes, such as Zener diode and board parasitic) to be accounted for arriving at exact value of C_GATE. The TIMER capacitor, C_T, must be programmed for timing greater than the total turnon time (t_ON), to ensure and avoid fault detection during start-up.

Typical application circuit with Gate Capacitor (dV/dt) Control Inrush Mode is shown in Figure 43. The turnon waveform with C_GATE of 4.7 nF and series resistor of 1 kΩ is shown in Figure 44.

Equation 15.

Figure 43. Gate Capacitor (dV/dt) Control Inrush Mode.