9.3.1 Enable and Adjusting Undervoltage Lockout

The EN/UVLO pin controls the ON and OFF state of the internal FET. A voltage V_(EN/UVLO) < V_(ENF) on this pin turns off the internal FET, thus disconnecting IN from OUT, while voltage below 0.6 V takes the device into shutdown mode, with I_Q less than 20 µA to ensure minimal power loss. Cycling EN/UVLO low and then back high resets the TPS2594xL that has latched off due to a fault condition.

The internal de-glitch delay on EN/UVLO falling edge is kept low for quick detection of power failure. For applications where a higher de-glitch delay on EN/UVLO is desired, or when the supply is particularly noisy, it is recommended to use an external bypass capacitor from EN/UVLO terminal to GND.

The undervoltage lock out can be programmed by using an external resistor divider from supply IN terminal to EN/UVLO terminal to GND as shown in Figure 50. When an undervoltage or input power fail event is detected, the internal FET is quickly turned off, and FLT is asserted. If the Under-Voltage Lock-Out function is not needed, the EN/UVLO terminal must be connected to the IN terminal. EN/UVLO terminal must not be left floating.

The device also implements internal undervoltage-lockout (UVLO) circuitry on the IN terminal. The device disables when the IN terminal voltage falls below internal UVLO Threshold V_(UVF). The internal UVLO threshold has a hysteresis of 115 mV.

Figure 50. UVLO and OVP Thresholds Set By R₁, R₂ and R₃

9.3.2 Overvoltage Protection (OVP)

The device incorporates circuit to protect system during overvoltage conditions. A resistor divider connected from the supply to OVP terminal to GND (as shown in Figure 50) programs the overvoltage threshold. A voltage more than V_(OVPR) on OVP pin turns off the internal FET and protects the downstream load. This pin must be tied to GND when not used.

9.3.3 Hot Plug-In and In-Rush Current Control

The device is designed to control the in-rush current upon insertion of a card into a live backplane or other "hot" power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended resets of the system power. A slew rate controlled start-up (dVdT) also helps to eliminate conductive and radiative interferences. An external capacitor connected from the dVdT pin to GND defines the slew rate of the output voltage at power-on (as shown in Figure 51). Equation governing slew rate at start-up is shown in Equation 1.

Figure 51. Output Ramp Up Time t_dVdT is Set by C_(dVdT)

Equation 1.

where

• I_(dVdT) = 1 µA (typical)
• = Desired output slew rate
• GAIN_(dVdT) = dVdT to OUT gain = 12

The total ramp time (t_dVdT) of V_(OUT) for 0 to V_(IN) can be calculated using Equation 2.

The inrush current, I_(INRUSH) can be calculated as shown in Equation 3.

The dVdT pin can be left floating to obtain a predetermined slew rate (t_dVdT) on the output. When terminal is left floating, the device sets an internal ramp rate of 30 V/ms for output (V_(OUT)) ramp.

Figure 61 and Figure 62 illustrate the inrush current control behavior of the TPS25942, TPS25944. For systems where load is present during start-up, the current never exceeds the overcurrent limit set by R_(ILIM) resistor for the application. For defining appropriate charging time/rate under different load conditions, see the Setting Output Voltage Ramp Time (tdVdT) section.

9.3.4 Overload and Short Circuit Protection

The device monitors load current by sensing the voltage across the internal sense resistor. The FET current is monitored at both the start-up and during normal operation. During overload events, the device keeps the over current limited to the overcurrent limit (I_(LIM)) programmed by R_(ILIM) resistor as shown in Equation 4.

Equation 4.

where

• I_(LIM) is overload current limit in Ampere.
• R_(ILIM) is the current limit resistor in kΩ

The device incorporates two distinct levels: an overcurrent-limit (I_(LIM)) and a fast-trip threshold (I_(FASTRIP)). The illustration of fast trip and current limit operation is shown in Figure 52.

Since the bias current on ILIM pin directly controls the current-limiting behavior of the device, the PCB routing of this node must be kept away from any noisy (switching) signals.

9.3.4.4 Constant Current Limit Behavior During Overcurrent Faults

If during current limit, power dissipation of the internal FET P_D = (V_(IN) – V_(OUT)) × I_(OUT)] exceeds 10 W, there is an approximately 0% to 5% thermal fold back in the current limit value so that I_(LIM) drops to I_OS. Eventually, the device shuts down due to over temperature.

Figure 52. Fast-Trip Current

9.3.5 Reverse Current Protection

A fast reverse comparator controls the internal FET and turns off the FET whenever the output voltage V_(OUT) exceeds the input voltage V_(IN) by 10 mV (typical) for 1 μs (typical). This prevents damage to the devices on the input side of the TPS2594xx by preventing significant current from sinking into the input side. However, a reverse current of (V_(OUT) - V_(IN))/ R_ON) should flow from the output to the input to establish reverse voltage V_(REVTH) of –10 mV across the device. The typical value of reverse current, needed for reverse voltage detection is –10 mV/ 42 mΩ = –238 mA

In power muxing applications, the reverse current magnitude I_(REV) depends on the slew-rate of the output voltage V_(OUT) and the system input capacitance C_IN as shown in Equation 5.

Equation 5.

For example, if the ramp rate of the output voltage is set at 10 mV/ μs then the required input capacitance C_IN to achieve reverse current greater than 238 mA is 23.8 µF. Considering tolerance of ±10% in capacitance and a standard value, capacitor of 33 µF should be used as C_IN in this case.

9.3.6 FAULT Response

The FLT open-drain output is asserted (active low) during undervoltage, overvoltage, reverse voltage-current and thermal shutdown conditions. Additionally, in the TPS25944, the FLT is asserted when overload condition exists for more than the fault time period (t_CB(dly)). The FLT signal remains asserted until the fault condition is removed and the device resumes normal operation. The device is designed to eliminate false fault reporting by using an internal "de-glitch" circuit for undervoltage and overvoltage (2.2-µs typical) conditions without the need for external circuitry. This ensures that fault is not accidentally asserted during transients on input bus.

Connect FLT with a pull up resistor to Input or Output voltage rail. FLT may be left open or tied to ground when not used. V_(IN) falling below V_(UVF) = 2.1 V resets FLT.

9.3.7 Current Monitoring

The current source at IMON terminal is configured to be proportional to the current flowing from IN to OUT. This current can be converted to a voltage using a resistor R_(IMON) from IMON terminal to GND terminal. This voltage, computed using Equation 7, can be used as a means of monitoring current flow through the system.

The maximum voltage range for monitoring the current (V_(IMONmax)) is limited to minimum([V_(IN) – 2.2 V], 6 V) to ensure linear output. This puts limitation on maximum value of R_(IMON) resistor and is determined by Equation 6.

Equation 6.

The output voltage at IMON terminal is calculated from Equation 7.

Equation 7.

where

• GAIN_(IMON) = Gain factor I_(IMON):I_(OUT) = 52 µA/A
• I_(OUT) = Load current
• I_{(IMON_OS)} = 0.8 µA (typical)

This pin must not have a bypass capacitor to avoid delay in the current monitoring information.

The voltage at IMON pin can be digitized using an ADC (such as ADS1100, SBAS239) to read the current monitor information over an I2C bus.

9.3.8 Power Good Comparator

The devices incorporate a Power Good comparator for co-ordination of status to downstream DC-DC converters or system monitoring circuits. The comparator has an internal reference of V_(PGTHR) = 0.99 V at negative terminal and positive terminal PGTH can be utilized for monitoring of either input or output of the device. The comparator output PGOOD is an open-drain active high signal, which can be used to indicate the status to downstream units. PGOOD is asserted high when internal FET is fully enhanced and PGTH pin voltage is higher than internal reference V_(PGTHR).

The PGOOD signal has deglitch time incorporated to ensure that internal FET is fully enhanced before heavy load is applied by downstream converters. Rising deglitch delay is determined by Equation 8.

Connect the PGOOD pin with a pull up resistor to Input or Output voltage rail. PGOOD may be left open or tied to ground when not used.

9.3.9 IN, OUT and GND Pins

The device has multiple pins for input (IN) and output (OUT).

All IN pins must be connected together and to the power source. A ceramic bypass capacitor close to the device from IN to GND is recommended to alleviate bus transients. The recommended operating voltage range is 2.7 V-18 V.

Similarly all OUT pins must be connected together and to the load. V_(OUT) in the ON condition, is calculated using Equation 9.

Equation 9.

where, R_ON is the total ON resistance of the internal FET.

GND terminal is the most negative voltage in the circuit and is used as a reference for all voltage reference unless otherwise specified.

9.3.10 Thermal Shutdown

The device has built-in over temperature shutdown circuitry designed to disable the internal FET, if the junction temperature exceeds 160°C (typical). The TPS25942L, 44L version latches off the internal FET, whereas the TPS25942A, 44A commences an auto-retry cycle 128 ms after T_J < [T_(TSD) – 12°C]. During the thermal shutdown, the fault pin FLT pulls low to signal a fault condition.

9.4.1 Diode Mode

The device provides a Diode Mode, where the power path from IN to OUT acts as a non-ideal diode rather than a FET, as shown in Figure 53. This mode is activated through DMODE terminal. This is an active high terminal with internal pull-down. The terminal is useful in Power-Mux applications to switch over from master to slave supplies and vice-versa smoothly, when two supplies are within a diode drop of each other. A high at this terminal activates the non-ideal diode mode. In this mode, the circuit breaker functionality (TPS25944x) is disabled and the overload current limit is set to 50 % of current limit determined by R_(ILIM) resistor.

Figure 53. Diode Mode: IN to OUT Power Path

9.4.2 Shutdown Control

The internal FET and hence the load current can be remotely switched off by taking the UVLO pin below its 0.6 V threshold with an open collector or open drain device as shown in Figure 54. The device quiescent current is reduced to less than 20 µA in this state. Upon releasing the UVLO pin the device turns on with soft-start cycle.

Figure 54. Shutdown Control

9.4.3 Operational Differences Between the TPS25942 and TPS25944

The TPS25942 and TPS25944 respond differently to overload and short circuit conditions. The operational differences are explained in Table 1.