ZHCS922C May   2012  – October 2015 TPS54140A

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Slope Compensation Output Current
      3. 7.3.3  Pulse Skip Eco-mode
      4. 7.3.4  Bootstrap Voltage (BOOT)
      5. 7.3.5  Low Dropout Operation
      6. 7.3.6  Error Amplifier
      7. 7.3.7  Voltage Reference
      8. 7.3.8  Overload Recovery Circuit
      9. 7.3.9  Overcurrent Protection and Frequency Shift
      10. 7.3.10 Power Good (PWRGD Pin)
      11. 7.3.11 Overvoltage Transient Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation with VIN < 3.5 V (Minimum VIN)
      2. 7.4.2 Operation with EN Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjusting the Output Voltage
      2. 8.1.2 Enable and Adjusting Undervoltage Lockout
      3. 8.1.3 Slow Start/Tracking Pin (SS/TR)
      4. 8.1.4 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      5. 8.1.5 Selecting the Switching Frequency
      6. 8.1.6 How to Interface to RT/CLK Pin
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Selecting the Switching Frequency
        2. 8.2.2.2  Output Inductor Selection (LO)
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Catch Diode
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Slow Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Undervoltage Lock Out Set Point
        9. 8.2.2.9  Output Voltage and Feedback Resistors Selection
        10. 8.2.2.10 Compensation
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
      1. 8.3.1 Simple Small Signal Model for Peak Current Mode Control
      2. 8.3.2 Small Signal Model for Frequency Compensation
      3. 8.3.3 Small Signal Model for Loop Response
  9. 9 Power Supply Recommendations
    1. 9.1 Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Estimate
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Specifications

6.1 Absolute Maximum Ratings(1)

Over operating temperature range (unless otherwise noted).
MIN MAX UNIT
Input voltage VIN –0.3 47 V
EN(2) –0.3 5
BOOT 55
VSENSE –0.3 3
COMP –0.3 3
PWRGD –0.3 6
SS/TR –0.3 3
RT/CLK –0.3 3.6
Output voltage PH–BOOT 8 V
PH –0.6 47
PH, 10-ns Transient –2 47
Voltage Difference PAD to GND ±200 mV
Source current EN 100 μA
BOOT 100 mA
VSENSE 10 μA
PH Current Limit A
RT/CLK 100 μA
Sink current VIN Current Limit A
COMP 100 μA
PWRGD 10 mA
SS/TR 200 μA
Operating junction temperature –40 150 °C
Storage temperature –65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See the Enable and Adjusting Undervoltage Lockout section of this data sheet for details.

6.2 ESD Ratings

VALUE UNIT
DRC package (VSON)
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
DGQ package (MSOP)
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible if necessary precautions are taken.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible if necessary precautions are taken.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Supply input voltage range 3.5 42 V
VO Output voltage range 0.8 39 V

6.4 Thermal Information

THERMAL METRIC(1) TPS54140A UNIT
DGQ (MSOP) DRC (VSON)
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance (standard board) 52.3 45.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 46.3 51.9 °C/W
RθJB Junction-to-board thermal resistance 33 20.5 °C/W
ψJT Junction-to-top characterization parameter 1.6 0.8 °C/W
ψJB Junction-to-board characterization parameter 32.7 20.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.9 5.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

TJ = –40°C to 150°C, VIN = 3.5 to 42 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Operating input voltage 3.5 42 V
Internal undervoltage lockout threshold No voltage hysteresis, rising and falling 2.5 V
Shutdown supply current EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 42 V 1.3 4 μA
Operating : nonswitching supply current VSENSE = 0.83 V, VIN = 12 V, 25°C 116 136
ENABLE AND UVLO (EN PIN)
Enable threshold voltage No voltage hysteresis, rising and falling 1.11 1.25 1.36 V
Input current Enable threshold +50 mV –3.8 μA
Enable threshold –50 mV –0.9
Hysteresis current 1.91 2.95 3.99 μA
VOLTAGE REFERENCE
Voltage reference TJ = 25°C 0.792 0.8 0.808 V
0.784 0.8 0.816
HIGH-SIDE MOSFET
On-resistance VIN = 3.5 V, BOOT-PH = 3 V 300 mΩ
VIN = 12 V, BOOT-PH = 6 V 200 410
ERROR AMPLIFIER
Input current 50 nA
Error amplifier transconductance (gM) ±2 μA < I(COMP) < 2 μA, V(COMP) = 1 V 97 μS
Error amplifier transconductance (gM) during slow start ±2 μA < I(COMP) < 2 μA, V(COMP) = 1 V,
VSENSE = 0.4 V		 26 μS
Error amplifier dc gain VSENSE = 0.8 V 10000 V/V
Error amplifier bandwidth 2700 kHz
Error amplifier source/sink V(COMP) = 1 V, 100 mV overdrive ±7 μA
COMP to switch current transconductance 6 A/V
CURRENT LIMIT
Current limit threshold VIN = 12 V, TJ = 25°C 1.8 2.7 A
THERMAL SHUTDOWN
Thermal shutdown 182 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching Frequency Range using RT mode 100 2500 kHz
fSW Switching frequency RT = 200 kΩ 450 581 720 kHz
Switching Frequency Range using CLK mode 300 2200 kHz
Minimum CLK pulse width 40 ns
RT/CLK high threshold 1.9 2.2 V
RT/CLK low threshold 0.5 0.7 V
RT/CLK falling edge to PH rising edge delay Measured at 500 kHz with RT resistor in series 60 ns
PLL lock in time Measured at 500 kHz 100 μs
SLOW START AND TRACKING (SS/TR)
Charge current VSS/TR = 0.4 V 2 μA
SS/TR-to-VSENSE matching VSS/TR = 0.4 V 45 mV
SS/TR-to-reference crossover 98% nominal 1.0 V
SS/TR discharge current (overload) VSENSE = 0 V, V(SS/TR) = 0.4 V 112 μA
SS/TR discharge voltage VSENSE = 0 V 54 mV
POWER GOOD (PWRGD PIN)
VVSENSE VSENSE threshold VSENSE falling 92%
VSENSE rising 94%
VSENSE rising 109%
VSENSE falling 107%
Hysteresis VSENSE falling 2%
Output high leakage VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C 10 nA
On resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50 Ω
Minimum VIN for defined output V(PWRGD) < 0.5 V, I(PWRGD) = 100 μA 0.95 1.5 V

6.6 Typical Characteristics

TPS54140A rdson_tj_lvs795.gif Figure 1. ON Resistance vs Junction Temperature
TPS54140A imax_tj_lvs795.gif Figure 3. Switch Current Limit vs Junction Temperature
TPS54140A fs_rt_clk_lvs795.gif Figure 5. Switching Frequency vs RT/CLK Resistance High Frequency Range
TPS54140A ea_tj_lvs795.gif Figure 7. EA Transconductance During Slow Start vs Junction Temperature
TPS54140A en_tj_lvs795.gif Figure 9. EN Pin Voltage vs Junction Temperature
TPS54140A ic2_tj_lvs795.gif Figure 11. EN Pin Current vs Junction Temperature
TPS54140A ss_tr2_tj_lvs795.gif Figure 13. SS/TR Discharge Current vs Junction Temperature
TPS54140A icc_tj_lvs795.gif Figure 15. Shutdown Supply Current vs Junction Temperature
TPS54140A icc2_tj_lvs795.gif Figure 17. VIN Supply Current vs Junction Temperature
TPS54140A rdson2_tj_lvs795.gif Figure 19. PWRGD ON Resistance vs Junction Temperature
TPS54140A boot_tj_lvs795.gif Figure 21. BOOT-PH UVLO vs Junction Temperature
TPS54140A offset_vs_lvs795.gif Figure 23. SS/TR to VSENSE Offset vs VSENSE
TPS54140A vref_tj_lvs795.gif Figure 2. Voltage Reference vs Junction Temperature
TPS54140A fs_tj_lvs795.gif Figure 4. Switching Frequency vs Junction Temperature
TPS54140A C006_SLVS919.gif Figure 6. Switching Frequency vs RT/CLK Resistance Low Frequency Range
TPS54140A ea2_tj_lvs795.gif Figure 8. EA Transconductance vs Junction Temperature
TPS54140A ic_tj_lvs795.gif Figure 10. EN Pin Current vs Junction Temperature
TPS54140A ss_tr_tj_lvs795.gif Figure 12. SS/TR Charge Current vs Junction Temperature
TPS54140A fs_vsense_lvs795.gif Figure 14. Switching Frequency vs VSENSE
TPS54140A icc_vi_lvs795.gif Figure 16. Shutdown Supply Current vs Input Voltage (Vin)
TPS54140A icc_vi2_lvs795.gif Figure 18. VIN Supply Current vs Input Voltage
TPS54140A pwrgd_tj_lvs795.gif Figure 20. PWRGD Threshold vs Junction Temperature
TPS54140A uvlo_tj_lvs795.gif Figure 22. Input Voltage (UVLO) vs Junction Temperature
TPS54140A offset_tj_lvs795.gif Figure 24. SS/TR to VSENSE Offset vs Temperature
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