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ZHCS922C May 2012 – October 2015 TPS54140A

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DGQ|10
- MPDS043F
DRC|10
- MPDS117L

散热焊盘机械数据 (封装 | 引脚)

DGQ|10
- PPTD325B
DRC|10
- QFND013N

订购信息

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS54140A is a 42-V, 1.5-A, step-down regulator with an integrated high-side MOSFET. This device is typically used to convert a higher DC voltage to a lower DC voltage with a maximum available output current of 1.5 A. Example applications are 12-V, 24-V and 48-V Industrial, Automotive and Commercial power systems. Use the following design procedure to select component values for the TPS54140A. This procedure illustrates the design of a high-frequency switching regulator. The Excel® spreadsheet (SLVC432) located on the product page can help on all calculations. Alternatively, use the WEBENCH software to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design.

8.1.1 Adjusting the Output Voltage

The output voltage is set with a resistor divider from the output node to the VSENSE pin. It is recommended to use 1% tolerance or better divider resistors. Start with a 10 kΩ for the R2 resistor and use the Equation 1 to calculate R1. To improve efficiency at light loads consider using larger value resistors. If the values are too high the regulator will be more susceptible to noise and voltage errors from the VSENSE input current will be noticeable

Equation 1. TPS54140A q_r1equalsr2_lvs795.gif

8.1.2 Enable and Adjusting Undervoltage Lockout

The TPS54140A is disabled when the VIN pin voltage falls below 2.5 V. If an application requires a higher undervoltage lockout (UVLO), use the EN pin as shown in Figure 28 to adjust the input voltage UVLO by using the two external resistors. Though it is not necessary to use the UVLO adjust registers, for operation providing a consistent power up behavior is recommended. The EN pin has an internal pull-up current source, I1, of 0.9 μA that provides the default condition of the TPS54140A operating when the EN pin floats. Once the EN pin voltage exceeds 1.25 V, an additional 2.9 μA of hysteresis, Ihys, is added. This additional current facilitates input voltage hysteresis. Use Equation 2 to set the external hysteresis for the input voltage. Use Equation 3 to set the input start voltage.

Figure 28. Adjustable Undervoltage Lockout (UVLO)

Equation 2. TPS54140A q_r1_lvs795.gif

Equation 3. TPS54140A q_r2_lvs795.gif

Another technique to add input voltage hysteresis is shown in Figure 29. This method may be used, if the resistance values are high from the previous method and a wider voltage hysteresis is needed. The resistor R3 sources additional hysteresis current into the EN pin.

Figure 29. Adding Additional Hysteresis

Equation 4. TPS54140A q_r1hyst_lvs795.gif

Equation 5. TPS54140A q_r2hyst_lvs795.gif

Do not place a low-impedance voltage source with greater than 5 V directly on the EN pin. Do not place a capacitor directly on the EN pin if V_EN > 5 V when using a voltage divider to adjust the start and stop voltage. The node voltage, (see Figure 30) must remain equal to or less than 5.8 V. The zener diode can sink up to 100 µA. The EN pin voltage can be greater than 5 V if the V_IN voltage source has a high impedance and does not source more than 100 µA into the EN pin.

Figure 30. Node Voltage

8.1.3 Slow Start/Tracking Pin (SS/TR)

The TPS54140A effectively uses the lower voltage of the internal voltage reference or the SS/TR pin voltage as the power-supply's reference voltage and regulates the output accordingly. A capacitor on the SS/TR pin to ground implements a slow start time. The TPS54140A has an internal pull-up current source of 2 μA that charges the external slow start capacitor. The calculations for the slow start time (10% to 90%) are shown in Equation 6. The voltage reference (V_REF) is 0.8 V and the slow start current (I_SS) is 2 μA. The slow start capacitor should remain lower than 0.47 μF and greater than 0.4 7nF.

Equation 6. TPS54140A q_css_lvs795.gif

At power up, the TPS54140A will not start switching until the slow start pin is discharged to less than 40 mV to ensure a proper power up, see Figure 31.

Also, during normal operation, the TPS54140A stops switching and the SS/TR must be discharged to 40 mV when the voltage at the VIN pin is below the VIN UVLO, EN pin pulled below 1.25 V, or a thermal shutdown event occurs.

The VSENSE voltage will follow the SS/TR pin voltage with a 45-mV offset up to 85% of the internal voltage reference. When the SS/TR voltage is greater than 85% on the internal reference voltage the offset increases as the effective system reference transitions from the SS/TR voltage to the internal voltage reference (see Figure 23). The SS/TR voltage will ramp linearly until clamped at 1.7 V.

Figure 31. Operation of SS/TR Pin when Starting

8.1.4 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)

The switching frequency of the TPS54140A is adjustable over a wide range from approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5 V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 7 or the curves in Figure 32 or Figure 33. To reduce the solution size one would typically set the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time should be considered.

The minimum controllable on time is typically 130 ns and limits the maximum operating input voltage.

The maximum switching frequency is also limited by the frequency shift circuit. More discussion on the details of the maximum switching frequency is located below.

Equation 7. TPS54140A q_rrt_lvs795.gif

Figure 32. Switching Frequency vs RT/CLK Resistance High Frequency Range

Figure 33. Switching Frequency vs RT/CLK Resistance Low Frequency Range

8.1.5 Selecting the Switching Frequency

The switching frequency that is selected should be the lower value of the two equations, Equation 8 and Equation 9. Equation 8 is the maximum switching frequency limitation set by the minimum controllable on time. Setting the switching frequency above this value will cause the regulator to skip switching pulses.

Equation 9 is the maximum switching frequency limit set by the frequency shift protection. To have adequate output short circuit protection at high input voltages, the switching frequency should be set to be less than the fsw(maxshift) frequency. In Equation 9, to calculate the maximum switching frequency one must take into account that the output voltage decreases from the nominal voltage to 0 volts, the fdiv integer increases from 1 to 8 corresponding to the frequency shift.

In Figure 34, the solid line illustrates a typical safe operating area regarding frequency shift and assumes the output voltage is zero volts, and the resistance of the inductor is 0.1 Ω, FET on resistance of 0.2Ω and the diode voltage drop is 0.5 V. The dashed line is the maximum switching frequency to avoid pulse skipping. Enter these equations in a spreadsheet or other software or use the SwitcherPro design software to determine the switching frequency.

Equation 8. TPS54140A q_fswmaxskip_lvs795.gif

Equation 9. TPS54140A q_fswmaxshift_lvs795.gif

I_L	inductor current
Rdc	inductor resistance
V_IN	maximum input voltage
V_OUT	output voltage
V_OUTSC	output voltage during short
Vc	diode voltage drop
R_DS(on)	switch on resistance
t_ON(min)	minimum controllable on time
ƒ_DIV	frequency divide equals (1, 2, 4, or 8)

Figure 34. Maximum Switching Frequency vs. Input Voltage

8.1.6 How to Interface to RT/CLK Pin

The RT/CLK pin can be used to synchronize the regulator to an external system clock. To implement the synchronization feature connect a square wave to the RT/CLK pin through the circuit network shown in Figure 35. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on time greater than 40 ns and an off time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200 kHz. The rising edge of the PH will be synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit should be designed in such a way that the device will have the default frequency set resistor connected from the RT/CLK pin to ground should the synchronization signal turn off. It is recommended to use a frequency set resistor connected as shown in Figure 35 through a 50Ω resistor to ground. The resistor should set the switching frequency close to the external CLK frequency. It is recommended to ac couple the synchronization signal through a 10 pF ceramic capacitor to RT/CLK pin and a 4kΩ series resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLK threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5V voltage source is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then will increase or decrease the switching frequency until the PLL locks onto the CLK frequency within 100 microseconds.

When the device transitions from the PLL to resistor mode the switching frequency will slow down from the CLK frequency to 150 kHz, then reapply the 0.5 V voltage and the resistor will then set the switching frequency. The switching frequency is divided by 8, 4, 2, and 1 as the voltage ramps from 0 to 0.8 volts on VSENSE pin. The device implements a digital frequency shift to enable synchronizing to an external clock during normal startup and fault conditions. Figure 36, Figure 37 and Figure 38 show the device synchronized to an external system clock in continuous conduction mode (ccm) discontinuous conduction (dcm) and pulse skip mode (psm).

Figure 35. Synchronizing to a System Clock

Figure 36. Plot of Synchronizing in CCM

Figure 38. Plot of Synchronizing in PSM

Figure 37. Plot of Synchronizing in DCM

8.2 Typical Application

Figure 39. High Frequency, 3.3V Output Power Supply Design with Adjusted UVLO

8.2.1 Design Requirements

This example details the design of a high frequency switching regulator design using ceramic output capacitors. A few parameters must be known in order to start the design process. These parameters are typically determined at the system level. For this example, we will start with the following known parameters:

Table 1. Design Parameters

DESIGN PARAMETER	EXAMPLE VALUE
Output Voltage	3.3 V
Transient Response 0 to 1.5-A load step	ΔVout = 4%
Maximum Output Current	1.5 A
Input Voltage	12 V nom. 8V to 18V
Output Voltage Ripple	< 33 mV_pp
Start Input Voltage (rising VIN)	7.7 V
Stop Input Voltage (falling VIN)	6.7 V

8.2.2 Detailed Design Procedure

8.2.2.1 Selecting the Switching Frequency

The first step is to decide on a switching frequency for the regulator. Typically, the user will want to choose the highest switching frequency possible since this will produce the smallest solution size. The high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage and the output voltage and the frequency shift limitation.

Equation 8 and Equation 9 must be used to find the maximum switching frequency for the regulator, choose the lower value of the two equations. Switching frequencies higher than these values will result in pulse skipping or the lack of overcurrent protection during a short circuit.

The typical minimum on time, t_onmin, is 130 ns for the TPS54140A. For this example, the output voltage is 3.3 V and the maximum input voltage is 18 V, which allows for a maximum switch frequency up to 1600 kHz when including the inductor resistance, on resistance and diode voltage in Equation 8. To ensure overcurrent runaway is not a concern during short circuits in your design use Equation 9 or the solid curve in Figure 34 to determine the maximum switching frequency. With an maximum input voltage of 20 V, assuming a diode voltage of 0.5V, inductor resistance of 100 mΩ, switch resistance of 200 mΩ, an output current of 2.8 A, the maximum switching frequency is approximately 1600kHz.

Choosing the lower of the two values and adding some margin a switching frequency of 1200kHz is used. To determine the timing resistance for a given switching frequency, use Equation 7 or the curve in Figure 32.

The switching frequency is set by resistor R_t shown in Figure 39.

8.2.2.2 Output Inductor Selection (L_O)

To calculate the minimum value of the output inductor, use Equation 10.

K_IND is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.

The inductor ripple current will be filtered by the output capacitor. Therefore, choosing high inductor ripple currents will impact the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. In general, the inductor ripple value is at the discretion of the designer; however, the following guidelines may be used.

For designs using low ESR output capacitors such as ceramics, a value as high as K_IND = 0.3 may be used. When using higher ESR output capacitors, K_IND = 0.2 yields better results. Since the inductor ripple current is part of the PWM control system, the inductor ripple current should always be greater than 100 mA for dependable operation. In a wide input voltage regulator, it is best to choose an inductor ripple current on the larger side. This allows the inductor to still have a measurable ripple current with the input voltage at its minimum.

For this design example, use K_IND = 0.2 and the minimum inductor value is calculated to be 7.6 μH. For this design, a nearest standard value was chosen: 10 μH. For the output filter inductor, it is important that the RMS current and saturation current ratings not be exceeded. The RMS and peak inductor current can be found from Equation 12 and Equation 13.

For this design, the RMS inductor current is 1.506 A and the peak inductor current is 1.62 A. The chosen inductor is a MSS6132-103. It has a saturation current rating of 1.64 A and an RMS current rating of 1.9 A.

As the equation set demonstrates, lower ripple currents will reduce the output voltage ripple of the regulator but will require a larger value of inductance. Selecting higher ripple currents will increase the output voltage ripple of the regulator but allow for a lower inductance value.

The current flowing through the inductor is the inductor ripple current plus the output current. During power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated above. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative approach is to specify an inductor with a saturation current rating equal to or greater than the switch current limit rather than the peak inductor current.

Equation 10. TPS54140A q_lomin_lvs795.gif

Equation 11. TPS54140A q_iripple_lvs795.gif

Equation 12. TPS54140A q_ilrms_lvs795.gif

Equation 13. TPS54140A q_ileak_lvs795.gif

8.2.2.3 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor will determine the modulator pole, the output voltage ripple, and how the regulators responds to a large change in load current. The output capacitance needs to be selected based on the more stringent of these three criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor needs to supply the load with current when the regulator can not. This situation would occur if there are desired hold-up times for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator also will temporarily not be able to supply sufficient output current if there is a large, fast increase in the current needs of the load such as transitioning from no load to a full load. The regulator usually needs two or more clock cycles for the control loop to see the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of droop in the output voltage. Equation 14 shows the minimum output capacitance necessary to accomplish this.

Where ΔIout is the change in output current, ƒsw is the regulators switching frequency and ΔVout is the allowable change in the output voltage. For this example, the transient load response is specified as a 4% change in Vout for a load step from 0A (no load) to 1.5 A (full load). For this example, ΔIout = 1.5-0 = 1.5 A and ΔVout = 0.04 × 3.3 = 0.132 V. Using these numbers gives a minimum capacitance of 18.9 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation. Aluminum electrolytic and tantalum capacitors have higher ESR that should be taken into account.

The catch diode of the regulator can not sink current so any stored energy in the inductor will produce an output voltage overshoot when the load current rapidly decreases, see Figure 40. The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high load current to a lower load current. The excess energy that gets stored in the output capacitor will increase the voltage on the capacitor. The capacitor must be sized to maintain the desired output voltage during these transient periods. Equation 15 is used to calculate the minimum capacitance to keep the output voltage overshoot to a desired value. Where L is the value of the inductor, I_OH is the output current under heavy load, I_OL is the output under light load, Vƒ is the final peak output voltage, and Vi is the initial capacitor voltage. For this example, the worst case load step will be from 1.5 A to 0 A. The output voltage will increase during this load transition and the stated maximum in our specification is 4% of the output voltage. This will make Vƒ = 1.04 × 3.3 = 3.432. Vi is the initial capacitor voltage which is the nominal output voltage of 3.3 V. Using these numbers in Equation 15 yields a minimum capacitance of 25.3 μF.

Equation 16 calculates the minimum output capacitance needed to meet the output voltage ripple specification. Where fsw is the switching frequency, V_oripple is the maximum allowable output voltage ripple, and I_ripple is the inductor ripple current. Equation 17 yields 0.7 μF.

Equation 17 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 17 indicates the ESR should be less than 144mΩ.

The most stringent criteria for the output capacitor is 25.3 μF of capacitance to keep the output voltage in regulation during an unload transient.

Additional capacitance de-ratings for aging, temperature and dc bias should be factored in which will increase this minimum value. For this example, a 47 μF 6.3V X7R ceramic capacitor with 5 mΩ of ESR will be used.

Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 18 can be used to calculate the RMS ripple current the output capacitor needs to support. For this application, Equation 18 yields 66mA.

Equation 14. TPS54140A q_cout1_lvs795.gif

Equation 15. TPS54140A q_cout2_lvs795.gif

Equation 16. TPS54140A q_cout3_lvs795.gif

Equation 17. TPS54140A q_resr_lvs795.gif

Equation 18. TPS54140A q_icoutrms_lvs795.gif

8.2.2.4 Catch Diode

The TPS54140A requires an external catch diode between the PH pin and GND. The selected diode must have a reverse voltage rating equal to or greater than Vinmax. The peak current rating of the diode must be greater than the maximum inductor current. The diode should also have a low forward voltage. Schottky diodes are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator will be.

Typically, the higher the voltage and current ratings the diode has, the higher the forward voltage will be. Since the design example has an input voltage up to 18 V, a diode with a minimum of 20 V reverse voltage will be selected.

For the example design, the B220A Schottky diode is selected for its lower forward voltage and it comes in a larger package size which has good thermal characteristics over small devices. The typical forward voltage of the B220A is 0.50 volts.

The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode which equals the conduction losses of the diode. At higher switch frequencies, the ac losses of the diode need to be taken into account. The ac losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery. Equation 19 is used to calculate the total power dissipation, conduction losses plus ac losses, of the diode.

The B220A has a junction capacitance of 120 pF. Using Equation 19, the selected diode will dissipate 0.632 Watts. This power dissipation, depending on mounting techniques, should produce a 16°C temperature rise in the diode when the input voltage is 18V and the load current is 1.5 A.

If the power supply spends a significant amount of time at light load currents or in sleep mode consider using a diode which has a low leakage current and slightly higher forward voltage drop.

Equation 19. TPS54140A q_pd_lvs795.gif

8.2.2.5 Input Capacitor

The TPS54140A requires a high quality ceramic, type X5R or X7R, input decoupling capacitor of at least 3 μF of effective capacitance and in some applications a bulk capacitance. The effective capacitance includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54140A. The input ripple current can be calculated using Equation 20.

The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the dc bias taken into account. The capacitance value of a capacitor decreases as the dc bias across a capacitor increases.

For this example design, a ceramic capacitor with at least a 20 V voltage rating is required to support the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16V, 25 V, 50 V or 100V so a 25 V capacitor should be selected. For this example, two 2.2 μF, 25 V capacitors in parallel have been selected. Table 2 shows a selection of high voltage capacitors. The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 21. Using the design example values, Ioutmax = 1.5 A, Cin = 4.4 μF, ƒsw = 1200 kHz, yields an input voltage ripple of 71 mV and a rms input ripple current of 0.701 A.

Equation 20. TPS54140A q_isirms_lvs795.gif

Equation 21. TPS54140A q_deltavin_lvs795.gif

Table 2. Capacitor Types

VENDOR	VALUE (μF)	EIA Size	VOLTAGE	DIALECTRIC	COMMENTS
Murata	1.0 to 2.2	1210	100 V	X7R	GRM32 series
	1.0 to 4.7	1210	50 V		GRM32 series
	1.0	1206	100 V		GRM31 series
	1.0 to 2.2	1206	50 V		GRM31 series
Vishay	1.0 10 1.8	2220	50 V		VJ X7R series
	1.0 to 1.2	2220	100 V
	1.0 to 3.9	2225	50 V
	1.0 to 1.8	2225	100 V
TDK	1.0 to 2.2	1812	100 V		C series C4532
	1.5 to 6.8	1812	50 V		C series C4532
	1.0. to 2.2	1210	100 V		C series C3225
	1.0 to 3.3	1210	50 V		C series C3225
AVX	1.0 to 4.7	1210	50 V		X7R dielectric series
	1.0	1210	100 V
	1.0 to 4.7	1812	50 V
	1.0 to 2.2	1812	100 V

8.2.2.6 Slow Start Capacitor

The slow start capacitor determines the minimum amount of time it will take for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This is also used if the output capacitance is very large and would require large amounts of current to charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54140A reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.

The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 22 can be used to find the minimum slow start time, tss, necessary to charge the output capacitor, Cout, from 10% to 90% of the output voltage, Vout, with an average slow start current of Issavg. In the example, to charge the 47 μF output capacitor up to 3.3 V while only allowing the average input current to be 0.125 A would require a 1 ms slow start time.

Once the slow start time is known, the slow start capacitor value can be calculated using Equation 6. For the example circuit, the slow start time is not too critical since the output capacitor value is 47 μF which does not require much current to charge to 3.3 V. The example circuit has the slow start time set to an arbitrary value of 1ms which requires a 3.3 nF capacitor.

Equation 22. TPS54140A q_tss_lvs795.gif

8.2.2.7 Bootstrap Capacitor Selection

A 0.1-μF ceramic capacitor must be connected between the BOOT and PH pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. The capacitor should have a 10-V or higher voltage rating.

8.2.2.8 Undervoltage Lock Out Set Point

The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54140A. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start switching once the input voltage increases above 7.7 V (enabled). After the regulator starts switching, it should continue to do so until the input voltage falls below 6.7 V (UVLO stop).

The programmable UVLO and enable voltages are set using a resistor divider between Vin and ground to the EN pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary. For the example application, a 332 kΩ between Vin and EN and a 61.9 kΩ between EN and ground are required to produce the 7.7 and 6.7 volt start and stop voltages.

8.2.2.9 Output Voltage and Feedback Resistors Selection

For the example design, 10.0 kΩ was selected for R2. Using Equation 1, R1 is calculated as 31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to current leakage of the VSENSE pin, the current flowing through the feedback network should be greater than 1 μA in order to maintain the output voltage accuracy. This requirement makes the maximum value of R2 equal to 800 kΩ. Choosing higher resistor values will decrease quiescent current and improve efficiency at low output currents but may introduce noise immunity problems.

8.2.2.10 Compensation

There are several industry techniques used to compensate DC/DC regulators. The method presented here yields high phase margins. For most conditions, the regulator will have a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54140A. Since the slope compensation is ignored, the actual cross over frequency is usually lower than the cross over frequency used in the calculations.

Use SwitcherPro software for a more accurate design.

The uncompensated regulator will have a dominant pole, typically located between 300 Hz and 3 kHz, due to the output capacitor and load resistance and a pole due to the error amplifier. One zero exists due to the output capacitor and the ESR. The zero frequency is higher than either of the two poles.

If left uncompensated, the double pole created by the error amplifier and the modulator would lead to an unstable regulator. To stabilize the regulator, one pole must be canceled out. One design approach is to locate a compensating zero at the modulator pole. Then select a cross over frequency that is higher than the modulator pole. The gain of the error amplifier can be calculated to achieve the desired cross over frequency. The capacitor used to create the compensation zero along with the output impedance of the error amplifier form a low frequency pole to provide a minus one slope through the cross over frequency. Then a compensating pole is added to cancel the zero due to the output capacitors ESR. If the ESR zero resides at a frequency higher than the switching frequency then it can be ignored.

To compensate the TPS54140A using this method, first calculate the modulator pole and zero using the following equations:

Equation 23. TPS54140A q_fpmod_lvs795.gif

where

I_OUT(max) is the maximum output current
C_OUT is the output capacitance
V_OUT is the nominal output voltage

Equation 24. TPS54140A q_fzmod_lvs795.gif

For the example design, the modulator pole is located at 1.5 kHz and the ESR zero is located at 338 kHz.

Next, the designer needs to select a crossover frequency which will determine the bandwidth of the control loop. The cross over frequency must be located at a frequency at least five times higher than the modulator pole. The cross over frequency must also be selected so that the available gain of the error amplifier at the cross over frequency is high enough to allow for proper compensation.

Equation 29 is used to calculate the maximum cross over frequency when the ESR zero is located at a frequency that is higher than the desired cross over frequency. This will usually be the case for ceramic or low ESR tantalum capacitors. Aluminum Electrolytic and Tantalum capacitors will typically produce a modulator zero at a low frequency due to their high ESR.

The example application is using a low ESR ceramic capacitor with 10 mΩ of ESR making the zero at 338 kHz.

This value is much higher than typical crossover frequencies so the maximum crossover frequency is calculated using both Equation 25 and Equation 28.

Using Equation 28 gives a minimum crossover frequency of 7.6 kHz and Equation 25 gives a maximum crossover frequency of 45.3 kHz.

A crossover frequency of 45 kHz is arbitrarily selected from this range.

For ceramic capacitors use Equation 25:

Equation 25. TPS54140A q_fcmax1_lvs795.gif

For tantalum or aluminum capacitors use Equation 26:

Equation 26. TPS54140A q_fcmax2_lvs795.gif

For all cases use Equation 27 and Equation 28:

Equation 27. TPS54140A q_fcmax3_lvs795.gif

Equation 28. TPS54140A q_fcmin_lvs795.gif

Once a cross over frequency, ƒc, has been selected, the gain of the modulator at the cross over frequency is calculated. The gain of the modulator at the cross over frequency is calculated using Equation 29 .

Equation 29. TPS54140A q_gmodfc_lvs795.gif

For the example problem, the gain of the modulator at the cross over frequency is 0.542. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole. However, calculating the values of these components varies depending on if the ESR zero is located above or below the cross over frequency. For ceramic or low ESR tantalum output capacitors, the zero will usually be located above the cross over frequency. For aluminum electrolytic and tantalum capacitors, the modulator zero is usually located lower in frequency than the cross over frequency. For cases where the modulator zero is higher than the cross over frequency (ceramic capacitors).

Equation 30. TPS54140A q_rc_lvs795.gif

Equation 31. TPS54140A q_cc_lvs795.gif

Equation 32. TPS54140A q_cf_lvs795.gif

For cases where the modulator zero is less than the cross over frequency (Aluminum or Tantalum capacitors), the equations are:

Equation 33. TPS54140A q_rc3_lvs795.gif

Equation 34. TPS54140A q_cc_lvs795.gif

Equation 35. TPS54140A q_cf3_lvs795.gif

For the example problem, the ESR zero is located at a higher frequency compared to the cross over frequency so Equation 32 through Equation 35 are used to calculate the compensation components. For the example problem, the components are calculated to be: R_C = 76.2 kΩ, C_C = 2710 pF, and Cƒ = 6.17 pF.

The calculated value of the Cƒ capacitor is not a standard value so a value of 2700 pF will be used. 6.8 pF is used for C_C. Rc resistor sets the gain of the error amplifier which determines the cross over frequency. The calculated R_C resistor is not a standard value, so 76.8kΩ will be used.

8.2.3 Application Curves

Figure 40. Load Transmit

Figure 42. VIN Power Up

Figure 44. Output Ripple, DCM

Figure 46. Input Ripple CCM

Figure 48. Input Ripple PSM

Figure 50. Overall Loop Frequency Response

Figure 52. Regulation vs Input Voltage

Figure 41. Startup With EN

Figure 43. Output Ripple CCM

Figure 45. Output Ripple, PSM

Figure 47. Input Ripple DCM

Figure 49. Efficiency vs Load Current

Figure 51. Regulation vs Load Current

8.3 System Examples

8.3.1 Simple Small Signal Model for Peak Current Mode Control

Figure 53 describes a simple small signal model that can be used to understand how to design the frequency compensation. The TPS54140A power stage can be approximated to a voltage-controlled current source (duty cycle modulator) supplying current to the output capacitor and load resistor. The control to output transfer function is shown in Equation 36 and consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current and the change in COMP pin voltage (node c in Figure 56) is the power stage transconductance. The gm_PS for the TPS54140A is 6 A/V. The low-frequency gain of the power stage frequency response is the product of the transconductance and the load resistance as shown in Equation 37.

As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with the load may seem problematic at first glance, but fortunately the dominant pole moves with the load current (see Equation 38). The combined effect is highlighted by the dashed line in the right half of Figure 53. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for the varying load conditions which makes it easier to design the frequency compensation. The type of output capacitor chosen determines whether the ESR zero has a profound effect on the frequency compensation design. Using high ESR aluminum electrolytic capacitors may reduce the number frequency compensation components needed to stabilize the overall loop because the phase margin increases from the ESR zero at the lower frequencies (see Equation 39).

Figure 53. Simple Small Signal Model and Frequency Response for Peak Current Mode Control

Equation 36. TPS54140A q_voovervc_lvs795.gif

Equation 37. TPS54140A eq15_lvs795.gif

Equation 38. TPS54140A q_fp_lvs795.gif

Equation 39. TPS54140A q_fz_lvs795.gif

8.3.2 Small Signal Model for Frequency Compensation

The TPS54140A uses a transconductance amplifier for the error amplifier and readily supports three of the commonly-used frequency compensation circuits. Compensation circuits Type 2A, Type 2B, and Type 1 are shown in Figure 54. Type 2 circuits most likely implemented in high bandwidth power-supply designs using low ESR output capacitors. The Type 1 circuit is used with power-supply designs with high-ESR aluminum electrolytic or tantalum capacitors.. Equation 40 and Equation 41 show how to relate the frequency response of the amplifier to the small signal model in Figure 54. The open-loop gain and bandwidth are modeled using the R_O and C_O shown in Figure 54. See Figure 39 for a design example using a Type 2A network with a low ESR output capacitor.

Equation 40 through Equation 49 are provided as a reference for those who prefer to compensate using the preferred methods. Those who prefer to use prescribed method use the method outlined in the application section or use switched information.

Figure 54. Types of Frequency Compensation

Figure 55. Frequency Response of the Type 2A and Type 2B Frequency Compensation

Equation 40. TPS54140A eq18_lvs795.gif

Equation 41. TPS54140A eq19_lvs795.gif

Equation 42. TPS54140A q_ea_lvs795.gif

Equation 43. TPS54140A eq21_lvs795.gif

Equation 44. TPS54140A eq22_lvs795.gif

Equation 45. TPS54140A q_p1_lvs795.gif

Equation 46. TPS54140A q_z1_lvs795.gif

Equation 47. TPS54140A eq25_lvs795.gif

Equation 48. TPS54140A eq26_lvs795.gif

Equation 49. TPS54140A eq27_lvs795.gif

8.3.3 Small Signal Model for Loop Response

Figure 56 shows an equivalent model for the TPS54140A control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gm_EA of 97 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor R_o and capacitor C_o model the open loop gain and frequency response of the amplifier. The 1mV ac voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting c/a shows the small signal response of the frequency compensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing R_L with a current source with the appropriate load step amplitude and step rate in a time domain analysis. This equivalent model is only valid for continuous conduction mode designs.

Figure 56. Small Signal Model for Loop Response