8.4.9 Synchronization and Stackable Configuration

The device can synchronize to an external clock which must be equal to or higher than internal frequency setting. For stand alone device, the external clock should be applied to the SYNC pin before VDD ramps up. A sudden change in synchronization clock frequency causes an associated control loop response, resulting in an overshoot or undershoot on the output voltage.

In dual phase stackable configuration:

1. when there is no external system clock applied, the master device will be configured as clock master, sending out pre-set switching frequency clock to slave device through SYNC pin. Slave receives this clock as switching clock with phase interleaving.
2. when a system clock is applied, both master and slave devices will be configured as clock slave, they sync to the external system clock as switching frequency with proper phase shift