The TPS544C26 device monitors the output voltage (VOSNS − GOSNS) to provide overvoltage (OV) and undervoltage (UV) protection. The Tracking OVF and Tracking UVF thresholds both track to the VOUT setting (commanded by either SVID SetVID command or I²C (A6h) VOUT_CMD) but can be selected independently.

VOUT Tracking UVF

The Table 7-11 shows the available tracking UVF thresholds. When the output voltage (VOSNS − GOSNS) drops below the VOUT setting by the value configured in (44h) VOUT_UV_FAULT_LIMIT register, the tracking UVF comparator detects and an internal UVF Response Delay counter selected in (45h) VOUT_UV_FAULT_RESPONSE register begins. At the same time, the UVF bit in (7Ah) STATUS_VOUT register is set. When the UVF Response Delay expires, the device responds to the UV fault per bit[3] RESTART selection in (45h) VOUT_UV_FAULT_RESPONSE register. With the RESTART bit unset (value "0"), the device latches OFF both high-side and low-side drivers. The latch is cleared with a reset of VCC or by re-toggling the EN pin. With the RESTART bit set (value "1"), the device enters hiccup mode and re-starts automatically after a hiccup sleep time of 56 ms, without limitation on the number of restart attempts.

The tracking UVF function is enabled only after the soft-start period completes.

During the UVF Response Delay, if the output voltage (VOSNS − GOSNS) rises above the UVF threshold, thus not qualified for a UVF event, the UVF response delay timer resets to zero. When the VOUT drops below the UVF threshold again, the UVF response delay timer re-starts from zero.

The TPS544C26 device also offers tracking UV Warning (UVW) function. The Table 7-12 shows the available tracking UVW thresholds. When the output voltage (VOSNS − GOSNS) drops lower than the VOUT setting by the value configured in (43h) VOUT_UV_WARN_LIMIT register, the tracking UVW comparator detects and the UVW bit in (7Ah) STATUS_VOUT register is set. There is no purpose delay for UVW event.

VOUT Tracking OVF

The Table 7-13 shows the available tracking OVF thresholds. When the output voltage (VOSNS − GOSNS) rises higher than the VOUT setting by the value configured in (40h) VOUT_OV_FAULT_LIMIT register, the tracking OVF comparator detects and the device responds to the OV fault immediately per bit[3] RESTART selection in (41h) VOUT_OV_FAULT_RESPONSE register. At the same time, the OVF bit in (7Ah) STATUS_VOUT register is set. With the RESTART bit unset (value "0"), the device latches OFF the high-side MOSFET driver and turns on the low-side MOSFET. The low-side MOSFET is kept ON until the sensed low-side negative current reaches the selected negative overcurrent (NOC) limit (see (B4h) IOUT_NOC_LIMIT register). Upon reaching the NOC limit, the low-side MOSFET is turned off, and the high-side MOSFET is turned on, for an on-time determined by PVIN, SEL_NOC_TON bit (see (ADh) COMP3) and f_SW setting. After the high-side MOSFET turns off the low-side MOSFET turns on again and the negative current on low-side MOSFET is monitored to compare with the selected NOC limit. The device operates in this cycle until the output voltage is fully discharged. Then the device has high-side MOSFET latched OFF and low-side MOSFET latched ON. The latch is cleared with a reset of VCC or by toggling the EN pin. With the RESTART bit set (value "1"), the device still discharge output voltage by the NOC operation. However, the device activates hiccup mode and re-starts automatically after a hiccup sleep time of 56 ms, without limitation on the number of restart attempts. The hiccup sleep time counter starts right after the OVF trigger.

The tracking OVF function is enabled only after the soft-start period completes.

The TPS544C26 device also offers tracking OV Warning (OVW) function. The Table 7-14 shows the available tracking OVW thresholds. When the output voltage (VOSNS − GOSNS) rises higher than the VOUT setting by the value configured in (42h) VOUT_OV_WARN_LIMIT register, the tracking OVW comparator detects and the OVW bit in (7Ah) STATUS_VOUT register is set. There is no purpose delay for OVW event.

VOUT Fixed OVF

In parallel with VOUT tracking OVF the TPS544C26 device offers Fixed OVF feature. The Fixed OVF comparator implments a constant reference which is configured in (B4h) IOUT_NOC_LIMIT register and the reference level does not track with the VOUT setting. The Fixed OVF comparator is activated to monitor the output voltage (VOSNS − GOSNS) all the time including power conversion off period (EN = low) and soft-start period. Once the VOUT Fixed OVF is triggered, the OVF bit in (7Ah) STATUS_VOUT register is set, and the device enters NOC operation immediately no matter the power conversion is enabled or not. The device operates in NOC operation to fully discharge the output voltage. Then the device has high-side MOSFET latched OFF and low-side MOSFET latched ON. The latch is cleared with a reset of VCC or by toggling the EN pin. A Fixed OVF event always leads to latch-off response and the selected OVF response in (41h) VOUT_OV_FAULT_RESPONSE register does not affect the response for a Fixed OVF event.

Given the Fixed OVF comparator is always activated the device provides alternate protection to high-side MOSFET damage cases. When the high-side MOSFET is damaged and short PVIN to the SW node, the output voltage (VOSNS − GOSNS) rises quickly. The TPS544C26 device can detect this kind of event and turn on low-side MOSFET to discharge the excess energy, thus protecting the load from damage.

In a case that the commanded VOUT is higher than the Fixed OVF threshold, the device triggers Fixed OV fault and enters the NOC operation immediately. If this scenario happens before soft-start, the device never initiate the soft-start ramp and enters latch-off directly. To avoid this situation, the Fixed OVF feature can be disabled through the bit[2] EN_FIX_OVF in (B4h) IOUT_NOC_LIMIT register.