The TPS544C26 device provides several options for
tuning the output voltage feedback and response to transients. Register (A9h) COMP1_MAIN,
(AAh) COMP2_MAIN and (ADh) COMP3 configure the control loop compensation through these
fields:
- DC Load Line: Selects the DC shift in
output voltage corresponding to increased output current. See (ADh) COMP3 for available options.
- AC Gain: The gain of the integration
and AC paths can be selected independently. The AC and integration gains both affect the
small-signal bandwidth of the converter. The higher AC Gain, the faster the control loop
responds to an output voltage error or a change on the current sense signal. Too high AC
Gain results in less noise immunity (a.k.a higher jitter). See (A9h) COMP1_MAIN for available options.
- AC Load Line (ACLL): Selects the AC
response to an output voltage error. Lower ACLL configuration directly improves the load
transient performance (less VOUT deviation). However, the control loop
becomes noise sensitive too low ACLL configuration. The ACLL also affects the settling
and response time following a load transient event. See (A9h) COMP1_MAIN for available options.
- Integration Gain: To maintain a good
VOUT regulation over load, the control loop includes an integration stage. Integration
Gain selects the gain of the integration stage which affects the loop response to an
output voltage error. Given the integration time constant is several times of switching
cycle time, the Integration Gain affects the loop gain in middle frequency range. The
gain of the integration and AC paths can be selected independently. The integration and
AC gains both affect the small-signal bandwidth of the converter. See (AAh) COMP2_MAIN for available options.
- Integration Time Constant: The
Integration Time Constant affects the settling and response time following an output
voltage error. See (AAh) COMP2_MAIN for available options.
- Ramp Amplitude: A ramp based on
PVIN/VOUT/fSW information is generated inside the IC to improve
jitter performance. Smaller ramp settings result in faster response to load transient
event, but also lead to increased off-time jitter. Likewise, large ramp settings result
in lower frequency jitter, but becomes slightly slower to respond to an output voltage
deviation. The ramp setting also affects the small-signal bandwidth of the converter.
See (AAh) COMP2_MAIN for available options.