Table 1. Design Parameters

PARAMETER	VALUE
Output Voltage	3.3 V
Transient Response 1.25 A to 3.75 A load step	ΔVOUT = 4 %
Maximum Output Current	5 A
Input Voltage	12 V nominal 6 V to 42 V
Output Voltage Ripple	0.5% of VOUT
Start Input Voltage (rising VIN)	5.75 V
Stop Input Voltage (falling VIN)	4.5 V

8.2.1.2.1 Custom Design with WEBENCH® Tools

Click here to create a custom design using the TPS54541 device with the WEBENCH® Power Designer.

1. Start by entering your V_IN, V_OUT, and I_OUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and compare this design with other possible solutions from Texas Instruments.
3. The WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real time pricing and component availability.
4. In most cases, you will also be able to:
   • Run electrical simulations to see important waveforms and circuit performance
   • Run thermal simulations to understand the thermal performance of your board
   • Export your customized schematic and layout into popular CAD formats
   • Print PDF reports for the design, and share your design with colleagues
5. Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.1.2.2 Selecting the Switching Frequency

Choose a switching frequency for the regulator. Typically, a designer uses the highest switching frequency possible because this produces the smallest solution size. High-switching frequency allows for lower-value inductors and smaller-output capacitors compared to a power supply that switches at a lower frequency. The switching frequency that can be selected is limited by the minimum on-time of the internal power switch, the input voltage, the output voltage, and the frequency-foldback protection.

Use Equation 12 and Equation 13 to calculate the upper limit of the switching frequency for the regulator. Choose the lower value result from the two equations. Switching frequencies higher than these values results in pulse skipping or the lack of overcurrent protection during a short circuit.

The typical minimum on time, t_onmin, is 135 ns for the TPS54541 device. For this example, the output voltage is 3.3 V and the maximum input voltage is 42 V. Assuming a diode voltage of 0.52 V, inductor DC resistance of 10.3 mΩ, typical switch resistance of 87 mΩ and 5-A load, from Equation 12 the maximum switch frequency to avoid pulse skipping is 680 kHz. To ensure overcurrent runaway is not a concern during short circuits, use Equation 10 to determine the maximum switching frequency for frequency foldback protection. With a current-limit value of 6.3 A and short circuit output voltage of 0.1 V, the maximum switching frequency is 960 kHz.

For this design, TI chose a lower-switching frequency of 400 kHz to operate below the calculated maximums. To determine the timing resistance for a given switching frequency, use Equation 10 or the curve in Figure 6. Figure 46 shows resistor R₃, which sets the switching frequency . For 400-kHz operation, the closest standard value resistor is 243 kΩ.

8.2.1.2.3 Output Inductor Selection (L_O)

To calculate the minimum value of the output inductor, use Equation 31.

K_IND is a ratio that represents the amount of inductor ripple current relative to the maximum output current. The inductor ripple current is filtered by the output capacitor. Choosing high inductor ripple currents impacts the selection of the output capacitor because the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. The inductor ripple value is at the discretion of the designer, but the following guidelines may be used.

For designs using low-ESR output capacitors such as ceramics, use a value as high as K_IND = 0.3. When using higher-ESR output capacitors, K_IND = 0.2 yields better results. Because the inductor ripple current is part of the current mode PWM control system, the inductor ripple current should always be greater than 150 mA for stable PWM operation. In a wide input voltage regulator, choose a relatively large inductor ripple current. This provides sufficient ripple current with the input voltage at the minimum.

For this design example, K_IND = 0.3 and the inductor value is calculated to be 5.1 μH. It is important that the RMS current and saturation current ratings of the inductor not be exceeded. See Equation 33 and Equation 34 for the RMS and peak inductor current. For this design, the RMS inductor current is 5 A and the peak inductor current is 5.79 A. The chosen inductor is a WE 744325550, which has a saturation current rating of 12 A and an RMS current rating of 10 A. This inductor also has a typical inductance of 5.5 µH at no load and 4.8 µH at 5-A load. Lastly, the inductor has a DCR of 10.3 mΩ.

As the equation set demonstrates, lower-ripple currents reduce the output voltage ripple of the regulator but require a larger value of inductance. Selecting higher-ripple currents increases the output voltage ripple of the regulator but allow for a lower-inductance value.

The current flowing through the inductor is the inductor ripple current plus the output current. During powerup, faults, or transient load conditions, the inductor current can increase above the peak inductor current level calculated previously. In transient conditions, the inductor current can increase up to the switch current limit of the device. For this reason, the most conservative design approach is to choose an inductor with a saturation current rating equal to or greater than the switch current limit of the TPS54541 device, which is nominally 7.5 A.

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8.2.1.2.4 Output Capacitor

There are three primary considerations for selecting the value of the output capacitor. The output capacitor determines the following:

• The modulator pole
• The output voltage ripple
• How the regulator responds to a large change in load current

Select the output capacitance based on the most stringent of these three criteria.

The desired response to a large change in the load current is the first criteria. The output capacitor must to supply the increased load current until the regulator responds to the load step. A regulator does not respond immediately to a large, fast increase in the load current such as transitioning from no load to a full load. The regulator usually requires two or more clock cycles for the control loop to sense the change in output voltage and adjust the peak switch current in response to the higher load. The output capacitance must be large enough to supply the difference in current for two clock cycles to maintain the output voltage within the specified range. Equation 35 shows the minimum output capacitance necessary, where ΔI_OUT is the change in output current, ƒsw is the switching frequency of the regulators and ΔV_OUT is the allowable change in the output voltage. For this example, the transient load response is specified as a 4% change in V_OUT for a load step from 1.25 A to 3.75 A. ΔI_OUT is 3.75 A – 1.25 A = 2.5 A and ΔV_OUT = 0.04 × 3.3 V = 0.13 V. These values provide a minimum capacitance of 95 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the ESR is usually small enough to be ignored. Aluminum electrolytic and tantalum capacitors have higher ESR that must be included in load step calculations.

The output capacitor must also be sized to absorb energy stored in the inductor when transitioning from a high to low load current. The catch diode of the regulator can not sink current so energy stored in the inductor can produce an output voltage overshoot when the load current rapidly decreases. Figure 51 shows a typical load step response. The excess energy absorbed in the output capacitor increases the voltage on the capacitor. The capacitor must be sized to maintain the output voltage during these transient periods. Equation 36 calculates the minimum capacitance required to keep the output voltage overshoot to a desired value, where L_O is the value of the inductor, I_OH is the output current under heavy load, I_OL is the output under light load, V_f is the peak output voltage and Vi is the initial voltage. For this example, the worst case load step is from 3.75 A to 1.25 A. The output voltage increases during this load transition and the stated maximum in our specification is 4% of the output voltage. This makes V_f = 1.04 × 3.3 V = 3.43 V. V_I is the initial capacitor voltage which is the nominal output voltage of 3.3 V. The values in Equation 36 yield a minimum capacitance of 68 μF.

Equation 37 calculates the minimum output capacitance needed to meet the output voltage ripple specification, where ƒsw is the switching frequency, V_ORIPPLE is the maximum allowable output voltage ripple, and I_RIPPLE is the inductor ripple current. Equation 37 yields 30 μF.

Equation 38 calculates the maximum ESR an output capacitor can have to meet the output voltage ripple specification. Equation 38 indicates the equivalent ESR should be less than 10 mΩ.

The most stringent criteria for the output capacitor is 95 μF required to maintain the output voltage within regulation tolerance during a load transient.

Capacitance de-ratings for aging, temperature, and DC bias increases this minimum value. For this example, two 100-μF 6.3-V type X5R ceramic capacitors with 2 mΩ of ESR are used. The derated capacitance is 130 µF, well above the minimum required capacitance of 95 µF.

Capacitors are generally rated for a maximum ripple current that can be filtered without degrading capacitor reliability, especially non ceramic capacitors. Some capacitor data sheets specify the Root Mean Square (RMS) value of the maximum ripple current. Equation 39 can calculate the RMS ripple current that the output capacitor must support. For this example, Equation 39 yields 460 mA.

8.2.1.2.5 Catch Diode

The TPS54541 device requires an external catch diode between the SW pin and GND. The selected diode must have a reverse voltage rating equal to or greater than V_IN(max). The peak current rating of the diode must be greater than the maximum inductor current. Schottky diodes are typically a good choice for the catch diode due to their low forward voltage. The lower the forward voltage of the diode, the higher the efficiency of the regulator.

Typically, diodes with higher voltage and current ratings have higher forward voltages. TI recommends a diode with a minimum of 42-V reverse voltage to allow input voltage transients up to the rated voltage of the TPS54541 device.

For the example design, the PDS760 Schottky diode is selected for its lower forward voltage and good thermal characteristics compared to smaller devices. The typical forward voltage of the PDS760 is 0.52 V at 5 A and 25°C.

The diode must also be selected with an appropriate power rating. The diode conducts the output current during the off-time of the internal power switch. The off-time of the internal switch is a function of the maximum input voltage, the output voltage, and the switching frequency. The output current during the off-time is multiplied by the forward voltage of the diode to calculate the instantaneous conduction losses of the diode. At higher switching frequencies, consider the AC losses of the diode. The AC losses of the diode are due to the charging and discharging of the junction capacitance and reverse recovery charge. Equation 40 calculates the total power dissipation, including conduction losses and AC losses of the diode.

The PDS760 diode has a junction capacitance of 180 pF. Using Equation 40, the total loss in the diode at the nominal input voltage is 1.89 W.

If the power supply spends a significant amount of time at light load currents or in sleep mode, consider using a diode, which has a low leakage current and slightly higher forward voltage drop.

8.2.1.2.6 Input Capacitor

The TPS54541 device requires a high-quality ceramic-type X5R or X7R input decoupling capacitor with at least 3 μF of effective capacitance. Some applications benefit from additional bulk capacitance. The effective capacitance includes any loss of capacitance due to DC bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple current rating greater than the maximum input current ripple of the TPS54541 device. Use Equation 41 to calculate the input ripple current.

The value of a ceramic capacitor varies significantly with temperature and the DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is more stable over temperature. X5R and X7R ceramic dielectrics are usually selected for switching regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor must also be selected with consideration for the DC bias. The effective value of a capacitor decreases as the DC bias across a capacitor increases.

For this example design, a ceramic capacitor with at least a 42-V voltage rating is required to support transients up to the maximum input voltage. Common standard ceramic capacitor voltage ratings include 4 V, 6.3 V, 10 V, 16 V, 25 V, 50 V, or 100 V. This example uses four 4.7-μF 50-V capacitors in parallel. Table 2 shows several choices of high-voltage capacitors.

The input capacitance value determines the input ripple voltage of the regulator. The maximum input voltage ripple occurs at 50% duty cycle and can be calculated using Equation 42. Using the design example values, I_OUT = 5 A, C_IN = 18.8 μF, ƒ_SW = 400 kHz, yields an input voltage ripple of 170 mV and a rms input ripple current of 2.5 A.

8.2.1.2.7 Slow-Start Capacitor

The slow-start capacitor determines the minimum amount of time for the output voltage to reach its nominal programmed value during power up. This is useful if a load requires a controlled voltage slew rate. This capacitor is also used if the output capacitance is large and would require large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54541 device reach the current limit or excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems.

The slow start time must be long enough to allow the regulator to charge the output capacitor up to the output voltage without drawing excessive current. Equation 43 can be used to find the minimum slow\-start time, T_ss, necessary to charge the output capacitor, C_OUT, from 10% to 90% of the output voltage, V_OUT, with an average slow start current of I_SSavg. In the example, to charge the effective output capacitance of 130 µF up to 3.3 V with an average current of 1 A requires a 0.3-ms slow-start time.

When the slow-start time is known, the slow-start capacitor value can be calculated using Equation 5. For the example circuit, the slow-start time is not critical because the output capacitor value is two-times 100 μF which does not require much current to charge to 3.3 V. The example circuit has the slow-start time set to an arbitrary value of 3.5 ms which requires a 9.3-nF slow-start capacitor calculated with Equation 44. For this design, the next larger standard value of 10 nF is used.

8.2.1.2.8 Bootstrap Capacitor Selection

A 0.1-μF ceramic capacitor must be connected between the BOOT and SW pins. TI recommends a ceramic capacitor with X5R or better grade dielectric. The capacitor must have a 10 V or higher voltage rating.

8.2.1.2.9 Undervoltage Lockout Set Point

The Undervoltage Lockout (UVLO) can be adjusted using an external voltage divider on the EN pin of the TPS54541 device. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the supply must turn on and start switching when the input voltage increases above 5.75 V (UVLO start). After the regulator starts switching, it must continue until the input voltage falls below 4.5 V (UVLO stop).

Programmable UVLO threshold voltages are set using the resistor divider of R_UVLO1 and R_UVLO2 between VIN and ground connected to the EN pin. Equation 3 and Equation 4 calculate the resistance values. For the example application, a 365 kΩ between V_IN and EN (R_UVLO1) and a 88.7 kΩ between EN and ground (R_UVLO2) are required to produce the 5.75-V and 4.5-V start and stop voltages.

8.2.1.2.10 Output Voltage and Feedback Resistors Selection

The voltage divider of R5 and R6 sets the output voltage. For the example design, 10.2 kΩ was selected for R6. Using Equation 2, R5 is calculated as 31.9 kΩ. The nearest standard 1% resistor is 31.6 kΩ. Due to the input current of the FB pin, the current flowing through the feedback network must be greater than 1 μA to maintain the accuracy of the output voltage. If the value of R6 is less than 800 kΩ, this requirement is satisfied. Choosing higher-resistor values decreases quiescent current and improves efficiency at low-output currents but may also introduce noise immunity problems.

8.2.1.2.11 Compensation

There are several methods to design compensation for DC-DC regulators. The method is simple to calculate and ignores the effects of the slope compensation that is internal to the device. Because the slope compensation is ignored, the actual crossover frequency is lower than the crossover frequency in the calculations. This method assumes the crossover frequency is between the modulator pole and the ESR zero and the ESR zero is at least ten-times greater the modulator pole.

To get started, calculate the modulator pole, ƒ_p(mod), and the ESR zero, ƒ_z1 using Equation 48 and Equation 49. For C_OUT, use a derated value of 130 μF. Use equations Equation 50 and Equation 51 to estimate a starting point for the crossover frequency, ƒ_co. For the example, design, ƒ_p(mod) is 1850 Hz and ƒ_z(mod) is 610 kHz. Equation 49 is the geometric mean of the modulator pole and the ESR zero and Equation 51 is the mean of modulator pole and half of the switching frequency. Equation 50 yields 34 kHz and Equation 51 gives 19 kHz. Use the geometric mean value of Equation 50 and Equation 51 for an initial crossover frequency. For this example, after lab measurement, the crossover frequency target increased to 30 kHz for an improved transient response.

Next, calculate the compensation components. A resistor in series with a capacitor creates a compensating zero. In parallel to these two components, a capacitor forms the compensating pole.

To determine the compensation resistor, R4, use Equation 52. The typical power stage transconductance, gmps, is 17 A/V. The output voltage, V_O, reference voltage, V_REF, and amplifier transconductance, gmea, are 3.3 V, 0.8 V and 350 μA/V, respectively. R4 is calculated to be 17 kΩ and a standard value of 16.9 kΩ is selected. Use Equation 53 to set the compensation zero to the modulator pole frequency. Equation 53 yields 5100 pF for compensating capacitor C5. 4700 pF is used for this design.

A compensation pole can be implemented by adding capacitor C8 in parallel with the series combination of R4 and C5. Use the larger value calculated from Equation 54 and Equation 55 for C8 to set the compensation pole. The value of C8 is 47 pF for this design example.

8.2.1.2.12 Power Dissipation Estimate

The following formulas estimate the TPS54541 power dissipation under CCM operation. Do not use these equations if the device is operating in DCM.

The power dissipation of the IC includes conduction loss (P_COND), switching loss (P_SW), gate drive loss (P_GD), and supply current (P_Q). Example calculations are shown with the 12-V typical input voltage of the design example.

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Therefore,

For given T_A,

For given T_J(MAX) = 150°C

Additional power loss occurs in the regulator circuit due to the inductor ac and dc losses and the catch diode and PCB trace resistance impacting the overall efficiency of the regulator.

8.2.1.2.13 Safe Operating Area

Figure 47 shows the safe operating area (SOA) of a typical design, through Figure 50 for 3.3-V, 5-V, and 12-V outputs and varying amounts of forced air flow. The temperature-derating curves represent the conditions at which the internal components and external components are at or below the maximum operating temperatures of the manufacturer. Derating limits apply to devices soldered directly to a double-sided PCB with 2-oz copper, similar to the EVM. Pay attention to the other components chosen for the design, especially the catch diode. In most applications, the thermal performance is limited by the catch diode. When operating at high-duty cycles or in the high end of the switching frequency range, the thermal performance of the TPS54541 can be the limiting factor.

8.2.1.2.14 Discontinuous Conduction Mode and Eco-mode Boundary

With an input voltage of 12 V, the power supply enters discontinuous conduction mode when the output current is less than 560 mA. The power supply enters Eco-mode when the output current is lower than 18 mA. The input current draw is 260 μA with no load.