7.3.1 2-Phase Application

Figure 23 shows the setup for a 2-phase application using two devices.

Figure 23. 2-Phase Application

7.3.2 Linear Regulators BP3 and BP6

The devices have two onboard linear regulators to provide suitable power for the internal circuitry of the device. Bypass the BP3 and BP6 pins externally for the converter to function properly. The BP3 pin requires a minimum of 2.2 µF of capacitance connected to AGND. The BP6 pin requires a minimum 2.2 µF of capacitance connected to PGND. TI recommends using a 4.7-µF capacitor and an additional 100-nF capacitor to reduce the ripple on the BP6 pin.

The use of the internal regulators to power other circuits is not recommended because the loads placed on the regulators might adversely affect operation of the controller.

7.3.3 Input Undervoltage Lockout (UVLO)

The devices provide flexible user adjustment of the undervoltage lockout (UVLO) threshold and hysteresis. Two PMBus commands, VIN_ON (35h) and VIN_OFF (36h), allow the user to independently set turnon and turnoff thresholds of these input voltages, with a minimum of 4-V turnoff to a maximum 7.75-V turnon. For more information, see Table 5.

7.3.4 Turnon and Turnoff Delay and Sequencing

The devices provide many sequencing options. Using the ON_OFF_CONFIG command, the device can be configured to start up whenever the input voltage is above the UVLO threshold, to require an additional signal on the CNTL pin, to receive an update to the OPERATION command through the PMBus interface, or a combination of these configurations. When the gating signal as specified by the ON_OFF_CONFIG command is asserted, a programmable turnon delay can be set with the TON_DELAY command to delay the start of regulation. Similarly, a programmable turnoff delay can be set with the TOFF_DELAY command to delay the stop of regulation once the gating signal is deasserted. Delay times are specified in milliseconds (ms), from 0 to 100 ms.

Figure 24 shows control of the start-up and shutdown operations of the device when the device is configured to respond to both the CNTL signal and the OPERATION command. The device can also be configured to independently use either the CNTL signal or the OPERATION command, or to convert power when a sufficient input voltage is available.

Figure 24. Turnon Controlled by Both Operation⁽¹⁾ and Control ^{Bit 7 of OPERATION is used to control power conversion.}

1. Bit 7 of OPERATION is used to control power conversion.

7.3.5 Voltage Reference

A reference digital-to-analog converter (DAC) with a 350-mV to 1650-mV range and 2^–9-V (1.953 mV) resolution connects to the noninverting input of the error amplifier. The tight tolerance on the reference voltage allows the user to design power supply with very-high DC accuracy.

7.3.6 Differential Remote Sense and Compensation

The devices implement a differential remote-sense amplifier to provide excellent load regulation by cancelling IR-drop in high-current applications. The RSP and RSN pins should be kelvin-connected to the output capacitor bank directly at the load, and routed back to the device as a tightly coupled differential pair. Ensure that these traces are isolated from fast switching signals and high current paths on the final PCB layout, as these can add differential-mode noise. Optionally, use a small coupling capacitor (1-nF typical) between the RSP and RSN pins to improve noise immunity. The output of the differential remote sense amplifier (DIFFO) is used for output voltage setting and error amplifier frequency compensation local to the device as shown in Figure 25.

The devices use voltage mode control with input feedforward. Frequency compensation can be accomplished using standard Type III techniques as shown in Figure 25.

In 2-phase configuration, the FB pin of the loop slave device should be tied to BP3 and the typical application circuit is shown in Figure 23. The loop master passes the internal COMP voltage through VSHARE pin to the loop slave device. For more information, see the Current Sharing section.

Additionally, the voltage at the DIFFO pin is digitized, averaged to reduce measurement noise and continually stored in the READ_VOUT command, enabling output voltage telemetry.

Figure 25. Output Voltage Setting

7.3.7 Set Output Voltage and Adaptive Voltage Scaling (AVS)

A voltage divider from the DIFFO pin to the FB pin is typically required to set the nominal output voltage like the one formed by R1 and R_BIAS resistors shown in Figure 25 and the resulted output voltage is shown in Equation 1.

Use Equation 3 to calculate the resulted internal-reference voltage.

The total adjustable range of the output voltage, including VOUT_COMMAND, MARGIN, and VREF_TRIM, is limited by the internal reference DAC of 0.35 V – 1.65 V . For more information on the implementation, see the Supported PMBus Commands section.

7.3.8 Reset VOUT

Without power cycling, the VOUT_COMMAND value and the corresponding output voltage can be reset to the default value which is latched when the devices are powered up from AVIN. When the RESET/PGD pin is pulled low, the digital core sets the VOUT_COMMAND value to the default value. Figure 26 shows the timing diagram for resetting the output voltage. When theRESET/PGD pin is asserted low, after a short delay (less than 2 µs), the output voltage begins to transition from the current value to the default VOUT_COMMAND value according to the slew-rate set in the VOUT_TRANSITION_RATE command. The VOUT_COMMAND value does not change to any values programmed in the VOUT_COMMAND register while the RESET/PGD pin is held low. The reset_vout status bit in the STATUS_MFR_SPECIFIC (80h) register is set for indication.

In the case of fault restart, the user has access to allow the VOUT_COMMAND value to be reset to the initial boot-up voltage by setting the RST_VOUT_oSD Bit in the OPTIONS (MFR_SPECIFIC_21) (E5h) register.

A. VOUT_COMMAND adjustment occurs through the PMBus interface.

B. Reset to the default VOUT_COMMAND value which is latched when the devices are powered up from AVIN. The slew rate is defined by the VOUT_TRANSITION_RATE comand.

Figure 26. Output Voltage Reset

7.3.9 Switching Frequency and Synchronization

A resistor from the RT pin (R_RT) to AGND sets the switching frequency. Use Equation 4 to calculate the R_RT resistor value.

Equation 4.

where

• R_RT is the timing resistor in Ohms
• f_SW is the switching frequency in Hertz

The devices are designed to operate from 200 kHz to 1 MHz.

7.3.9.1 Synchronization

The devices can synchronize to an external clock that is ±20% of the free-running frequency.

7.3.9.1.1 Stand-Alone Device

The device supports auto detection on the SYNC pin of the stand-alone device or the PWM-loop master device in a 2-phase configuration. With the external clock applied to the SYNC pin before AVIN power-up or pulling up the SYNC pin to the BP3 or BP6 pin, the SYNC pin is configured as SYNC-IN, and is synchronized to the rising edge of the external clock applied to this pin, with a minimum pulse width of 200 ns (maximum). If no external clock edges occur or logic-high voltage is applied to the SYNC pin at AVIN power-up, the SYNC pin is configured as SYNC-OUT, and the internal free-running frequency set by the RT resistor is output on the SYNC pin. A sudden change in synchronization clock frequency causes an associated control-loop response, resulting in an overshoot or undershoot on the output voltage.

7.3.9.1.2 Master-Slave Configuration

Without the requirement of an external clock, the SYNC pin of the PWM-loop master device can be configured as SYNC-OUT and output a 50% duty-cycle clock to the slave device. The slave device is then synchronized to the falling edge of the clock applied to the SYNC pin. Both the loop master and slave devices require an RT resistor to set the free-running frequency. Figure 27 shows the simplified schematic for this configuration. For the loop slave device in a 2-phase configuration, the SYNC pin is always configured as SYNC-IN, and is synchronized to the falling edge of the incoming clock on the SYNC pin. Figure 28 shows the timing for phase interleaving.

Figure 27. Master-Slave Synchronization and Phase Interleaving Setting

Figure 28. Phase Interleaving Timing

An external clock can optionally be applied to both the PWM-loop master and the slave device to synchronize the stack. Only 50% duty cycle of the external clock can be applied to the 2-phase stack to realize the interleaving of two phases. The loop master automatically (auto) detects if an external clock is available for synchronisation. One clock master can also sync another stack as shown in Figure 29. When the auto detection determines the clock master and clock slave, the configuration cannot change until AVIN power cycling.

The EEPROM setup (FORCE_SYNC_IN Bit and FORCE_SYNC_OUT Bit) overrides auto detection of the SYNC pin. Therefore, if the FORCE_SYNC_OUT Bit is set to 1, the user should not apply the external clock to SYNC pin, which may cause catastrophic damage to the device. The FORCE_SYNC_IN Bit has higher priority than the FORCE_SYNC_OUT Bit. Neither the FORCE_SYNC_IN Bit nor the FORCE_SYNC_OUT Bit are set as a factory-default setting.

Figure 29. Phase Interleaving Timing

7.3.9.1.3 SYNC Fault

The converter is allowed to stop switching after detecting the SYNC signal is expected, but not present or has been lost. The device also reports a live (essentially unlatched) sync_flt bit in the STATUS_MFR_SPECIFIC (80h) register. The SMBALERT is not triggered if the SYNC_FAULT bit goes high. The default SYNC fault response is as follows.

• For the case of a clock that is lost after it was previously present, the SYNC-loss detection latency is approximately 10 µs. During this delay time (between when the clock is lost to when the controller detects it), the clock slave (loop slave or loop master set as clock slave) continues to operate at a frequency that is approximately 40% less than the free-running frequency. The frequencies of two devices are most likely not identical during this 10-µs duration. The clock master continues to operate at the free-running frequency during the 10-µs duration.
• For the case of a clock signal that is never present, both phases (for 2-phase) or the standalone PWM-loop master (1-phase) remain off (never switch) while waiting for the external clock to arrive.

After the external clock is restored, seven clock cycles are counted and then the rail performs a new soft-start. No further user intervention (for example, power-cycle, CNTL toggle, CLEAR_FAULTS, or others) is required for the rail to start up after clock restoration

NOTE

The SYNC fault response can be disabled by setting the SYNC_FAULT_DIS Bit in the MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h) register. The SYNC_FAULT_DIS Bit, when set, disables the sync_flt reporting status, and the devices that lost the SYNC clock input (loop slave or loop master set clock slave) continue to operate at a frequency approximately 40% less than the free-running frequency for approximately 10 µs, then back to the free-running frequency without shutting down. But the frequencies of two devices are most likely not identical because the clock master continues to operate at its own free-running frequency.

7.3.10 Current Sharing

For two devices to operate in a 2-phase application, the SYNC, VSHARE, and ISHARE pins of both devices should be connected respectively, as shown in Figure 30. The loop master device shares the same VSHARE voltage. Essentially the internal COMP voltage is shared with the loop slave by connecting the VSHARE pin of each device together. The sensed current in each phase is compared first by connecting the ISHARE pin of each device, then the error current is added into the internal COMP. The resulting voltage is compared with the PWM ramp to generate the PWM pulse. This current sharing loop maintains the current balance between devices.

An additional resistor connected between the ISHARE pins of both devices can be used to lower the current-sharing loop gain for better stability margin. Use to calculate the current sharing gain (G_ISHARE).

Figure 30. Current Sharing

In addition to sharing the same internal COMP voltage, the VSHARE pin is also used for fault communication between the loop master and slave devices. The VSHARE pin voltage is pulled low if any device encounters any fault conditions so that the other device sharing VSHARE pin is alerted and stops switching accordingly.

An optional high-frequency capacitor can be added between the VSHARE pin and ground in noisy systems, but the capacitance should not exceed 10 pF.

7.3.11 Soft-Start Time and TON_RISE Command

To control the inrush current required to charge the output capacitor bank during start up, the devices implement a soft-start time. When the device is enabled, the feedback reference voltage, V_REF, ramps from 0 V to the final level defined by Equation 3 at a slew rate defined by the TON_RISE command. The specified rise times are defined by the slew rate required to ramp the reference voltage from 0 V to the final value at each given rise time.

The actual rise time of the converter output is slightly less than the rise time defined by the TON_RISE command. This difference occurs because switching does not occur until the error-amplifier output reaches the valley of the PWM ramp. During the soft-start time, the error-amplifier output voltage starts at 0 V and then begins switching again only when the VSHARE voltage reaches the valley of the PWM ramp which is 1.23 V (typical). When the VSHARE voltage reaches the valley of the PWM ramp, the converter output voltage rises quickly until the feedback voltage, V_FB, reaches the V_REF level, at which point they track through the end of the soft-start period.

Figure 31. Soft-Start Timing

The devices support several soft-start times from 1 ms to 100 ms which are selected by the TON_RISE command.

The value of TON_RISE comman can be set through the PMBus interface or alternatively by the resistor connected from the SS pin to AGND.

Table 3 lists the E48 series resistors with no worse than 1% tolerance suggested for the TON_RISE setting. Issuing a TON_RISE command after start-up overwrites the TON_RISE value set by the external resistor. If the device restarts after losing power completely, the TON_RISE value set by external resistor overwrites any value stored from previous the TON_RISE operation.

7.3.12 Prebiased Output Start-Up

The devices prevent current from being discharged from the output during start-up, when a prebiased output condition exists. If the output is prebiased, no SW pulses occur until the internal soft-start voltage rises above the error-amplifier input voltage (FB pin). As soon as the soft-start voltage exceeds the error-amplifier input, and SW pulses start and the device limits synchronous rectification after each SW pulse with a narrow on-time. The on-time of the low-side MOSFET slowly increases on a cycle-by-cycle basis until 128 pulses have been generated and the synchronous rectifier runs fully complementary to the high-side MOSFET. This approach prevents the sinking of current from a prebiased output, and ensures the output-voltage start-up and ramp-to-regulation sequences are smooth and monotonic.

For prebias that is higher than regulation, the PWM-loop master device is forced to go through the 128 cycles of prebias operation at the end of TON_RISE time.

The output overvoltage warn is tripped when the FB pin is prebiased to higher than 5% about the regulation level. These devices respond to a prebiased output overvoltage condition immediately upon AVIN powered up and when the BP6 regulator voltage is above the BP6 UVLO of 3.73 V (typical).

7.3.13 Soft-Stop time and TOFF_FALL Command

The devices implement the TOFF_FALL command to define the time for the output voltage to drop from regulation to 0 as shown in Figure 24. Negative current in the devices can occur during the TOFF_FALL time to discharge the output voltage. The setting of the TOFF_FALL command to 0 ms causes the unit to bring the output voltage down to 0 as quickly as possible, which results in an effective TOFF_FALL time of 1 ms (fastest time supported). This feature can be disabled in the ON_OFF_CONFIG command for the turnoff controlled by the CNTL pin or bit 6 of the OPERATION register if the regulator is turned off by the OPERATION command. If the regulator is turned off by the OPERATION command, both the high-side and low-side FET drivers are turned off immediately and the output voltage is discharged by the load.

7.3.14 Output Current Telemetry and Low-Side MOSFET Overcurrent Protection

7.3.14.1 Output Current Telemetry

The devices sense the average output current using an internal sense FET as shown in Figure 32. A sense FET conducts a scaled-down version of the power-stage current. Sampling this current in the middle of the low-side drive signal determines the average output current. This architecture achieves excellent current monitoring and better overcurrent threshold accuracy than the current sensing of a DC-resistance (DCR) inductor with minimal temperature variation and no dependence on power loss in a higher DCR inductor. Use the IOUT_CAL_OFFSET command to improve current sensing and overcurrent accuracy by removing systematic errors related to board layout after assembly. The devices continually digitize the sensed output current, and average it to reduce measurement noise. The devices then store the current value in the read-only register, READ_IOUT, which enables output-current telemetry.

Figure 32. SenseFET Average Current Sensing and Overcurrent Protection

7.3.15 High-Side MOSFET Short-Circuit Protection

The devices also implement a fixed high-side MOSFET overcurrent (HSOC) protection to limit peak current, and prevent inductor saturation in the event of a short circuit. The devices detect an overcurrent event by sensing the voltage drop across the high-side MOSFET when it is on. If the peak current reaches the I_HOSC level on any given cycle, the cycle terminates to prevent the current from increasing any further. High-side MOSFET overcurrent events are counted using the method shown in Figure 32. If the devices detect three consecutive overcurrent events (high-side or low-side), the converter responds by flagging the appropriate status registers, triggering the SMBALERT signal if it is not masked, and entering either continuous-restart-hiccup mode or latches off according to the IOUT_OC_FAULT_RESPONSE command. For accurate overcurrent protection for the high-side MOSFET, the PVIN and AVIN pins must have the same potential because split-rail operation is not supported. The IOUT_OC_FAULT_RESPONSE command can also be set to ignore the OC fault for debugging purposes. When the IOUT_OC_FAULT_RESPONSE command is set to ignore, the device continues to have cycle-by-cycle HSOC protection. Table 4 summarizes the fault-response scheme.

7.3.16 Die Temperature Telemetry and Overtemperature Protection

An internal temperature sensor based off the bandgap reference protects the devices from thermal runaway. The internal thermal shutdown threshold, T_SD, is fixed at 145°C (typical). When the devices sense a temperature above T_SD, an otf_bg bit in the STATUS_MFR_SPECIFIC command is flagged, and power conversion stops until the sensed junction temperature decreases by the amount of the thermal shutdown hysteresis, T_HYST (20°C typical). The SMBALERT signal is triggered if it is not masked.

The devices also provide temperature telemetry and programmable internal overtemperature fault or warning thresholds using measurements from an internal temperature sensor as shown in Figure 33. The temperature-sensor circuit applies two bias currents to an internal diode-connected NPN transistor, and measures ΔV_BE to infer the junction temperature of the sensor. The devices then digitize the result and compare it to the user-configured overtemperature fault and warning thresholds. When an internal overtemperature fault (OTF) is detected, power conversion stops until the sensed temperature decreases by 20°C. The READ_TEMPERATURE_1 (8Dh) register is continually updated with the digitized temperature measurement, enabling temperature telemetry. The OT_FAULT_LIMIT (4Fh) and OT_WARN_LIMIT (51h) commands set the overtemperature fault and warning thresholds through the PMBus interface. When an overtemperature event is detected, the device sets the appropriate flags in STATUS_TEMPERATURE (7Dh) command and triggers the SMBALERT signal if it is not masked.

The device response upon internal overtemperature fault can be set to Latch-off, Restart and Ignore in OT_FAULT_RESPONSE. The default response to an over temperature fault is to ignore. Fixed band gap-detected overtemperature (OT) faults are never ignored. The band gap OT faults always respond in a shutdown and attempted restart once the part cools. Table 4 summarizes the fault-response scheme.

Figure 33. Overtemperature Protection

7.3.17 Output Voltage Telemetry and Over-/Under-voltage Protection

7.3.18 TON_MAX Fault

The TON_MAX_FAULT_LIMIT command sets an upper limit, in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit. The devices differentiate a startup UV fault and a regulation UV fault by implementing the TON_MAX_FAULT_LIMIT command. The TON_MAX_FAULT_LIMIT command can allow the devices more time than the soft-start time defined by TON_RISE to come into regulation and the UV detection is essentially delayed up to the TON_MAX_FAULT_LIMIT time. For more details, see the TON_MAX_FAULT_LIMIT (62h) section.

7.3.19 Power Good (PGOOD) Indicator

When the output voltage remains within the PGOOD window after the start-up period, PGOOD as an open-drain output is released, and rises to an externally supplied logic level. The PGOOD window is defined by OV warning limit and UV warning limit in PCT_OV_UV_WRN_FLT_LIMITS (MFR_SPECIFIC_07) (D7h), which can be programmed through the PMBus interface, as shown in Figure 34. The PGOOD pin pulls low upon any fault condition on default. Please refer to Table 4 for the possible sources to pull down the PGOOD pin.

The PGOOD signal can be connected to the CNTL pin of another device to provide additional controlled turnon and turnoff sequencing.

The OVW or PGOOD signal trips when the FB pin is prebiased to higher than 5% about the regulation level. This level of prebias is unusual and it is beneficial to flag a warning in this situation.

Figure 34. PGOOD Threshold and Hysteresis

7.3.20 Fault Protection Responses

Table 4 summarizes the various fault protections and associated responses.

7.3.21 Switching Node

The SW pin connects to the switching node of the power-conversion stage and acts as the return path for the high-side gate driver. When configured as a synchronous buck stage, the voltage swing on SW normally traverses from below ground to well above the input voltage. Parasitic inductance in the high-side FET and the output capacitance (C_OSS) of both power FETs form a resonant circuit that can produce high frequency ( > 100 MHz) ringing on this node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the pin.

In many cases, a series resistor and capacitor snubber network connected from the switching node to PGND can be helpful in damping the ringing and decreasing the peak amplitude. Provide provisions for snubber network components in the layout of the printed circuit board. If testing reveals that the ringing amplitude at the SW pin exceeds the limit, then include snubber components. For more information about snubber circuits design, refer to Snubber Circuits: Theory, Design and Application (SLUP100).

Placing a BOOT resistor in series with the BOOT capacitor slows down the turnon of the high-side FET and can help to reduce the peak ringing at the switching node as well.

7.3.22 PMBus General Description

Timing and electrical characteristics of the PMBus interface specification can be found in the PMB Power Management Protocol Specification, Part 1, revision 1.3 available at http://pmbus.org. The devices support both the 100-kHz and 400-kHz bus timing requirements. The devices do not stretch pulses when communicating with the master device.

Communication over the PMBus interface can support the Packet Error Checking (PEC) scheme if desired. If the master supplies clock (CLK pin) pulses for the PEC byte, PEC is used. If the CLK pulses are not present before a STOP, the PEC is not used.

The devices support a subset of the commands in the PMBus 1.3 Power Management Protocol Specification. See Supported PMBus Commands for more information

The devices also support the SMBALERT response protocol. The SMBALERT response protocol is a mechanism by which a slave device (such as the devices ) can alert the bus master that it is available for communication. The master processes this event and simultaneously accesses all slaves on the bus (that support the protocol) through the alert response address (ARA). Only the slave that caused the alert acknowledges this request. The host performs a modified receive byte operation to ascertain the slave address. At this point, the master can use the PMBus status commands to query the slave that caused the alert. By default these devices implement the auto alert response, a manufacturer specific improvement to the SMBALERT response protocol, intended to mitigate the issue of bus hogging. For more information, see the Auto ARA Response section. For more information on the SMBus alert response protocol, refer to the System Management Bus (SMBus) specification.

The devices contain nonvolatile memory that stores configuration settings and scale factors. However, the device does not save the settings programmed into this nonvolatile memory. The STORE_DEFAULT_ALL (11h) or STORE_USER_ALL (11h) command must be used to commit the current settings to nonvolatile memory as device defaults. The settings that are capable of being stored in nonvolatile memory are noted in the detailed command descriptions.

7.3.23 PMBus Address

The PMBus specification requires that each device connected to the PMBus have a unique address on the bus. The has fixed PMBus addresses of 36 decimal for the loop master and 37 decimal for the loop slave device.

7.3.24 PMBus Connections

The devices support both the 100-kHz and 400-kHz bus speeds, 1.8-V or 3.3-V and 5-V PMBus-interface logic level. For more information, see the PMBus Interface section of the Specifications.

7.3.25 Auto ARA (Alert Response Address) Response

By default, the devices implement the auto alert response, a manufacturer specific improvement to the standard SMBALERT response protocol defined in the SMBus specification. The auto alert response is designed to prevent SMBALERT monopolizing in the case of a persistent fault condition on the bus. The user can choose to disable the auto ARA response, and use the standard SMBALERT response as defined in the SMBus specification, by using the EN_AUTO_ARA Bit of the OPTIONS (MFR_SPECIFIC_21) register.

In the case of a fault condition, the slave device experiencing the fault pulls down the shared SMBALERT line, to alert the host that a fault condition has occurred. To establish which slave device has experienced the fault, the host issues a modified receive byte operation to the alert response address (ARA), to which only the slave pulling down on SMBALERT should respond. The SMBus protocol provides a method for address arbitration in the case that multiple slaves on the same bus are experiencing fault conditions. When the host has established the address of the offending device, it must take any necessary action to release the SMBALERT line. For more information on the standard SMBus alert response protocol, refer to the SMBus specification.

In the case of a non-persistent fault (a single-time event, such as an invalid command or data byte), the host can ascertain the address of the slave experiencing a fault using the standard ARA response, and simply issue CLEAR_FAULTS to release the SMBALERT line, and resume normal operation. However, in the case of a persistent fault (one which remains active for some time, such as a short-circuit, or thermal shutdown), once the device issues a CLEAR_FAULTS command, the fault immediately re-triggers, and SMBALERT continues to be pulled low. In this case, the device holds low the SMBALERT line until the host masks the SMBALERT line using SMBALERT_MASK and then issues the CLEAR_FAULTS command. Because the SMBALERT line remains low, the host cannot be alerted to other fault conditions on the bus until it clears SMBALERT. Figure 35 and Figure 36 show this response.

Figure 35. Example Standard ARA Response to Nonpersistent Fault

Figure 36. Example Standard ARA Response to a Persistent Fault

To mitigate the problem of SMBALERT bus hogging described previously, the devices implement the Auto ARA response. When Auto ARA is enabled, the devices releases SMBALERT automatically after successfully responding to access from the host at the alert response address. In this case, even when the device is experiencing a persistent fault, it does not hold the SMBALERT line low following successful notification of the host, and the host can be alerted to other faults on the bus in the normal manner. Examples of the auto ARA response are shown in Figure 37 and Figure 38.

Figure 37. Example Auto ARA Response to Nonpersistent Fault

Figure 38. Example Auto ARA Response to Persistent Fault

7.4.1 Continuous Conduction Mode

The devices operate in continuous conduction mode (CCM) at a fixed frequency, regardless of the output current. For the first 128 switching cycles, the low-side MOSFET on-time is slowly increased to prevent excessive current sinking in the event the device is started with a prebiased output. Following the first 128 clock cycles, the low-side MOSFET and the high-side MOSFET on-times are fully complementary.

7.4.2 Operation with CNTL Signal Control

According to the value in the ON_OFF_CONFIG register, the devices can be commanded to use the CNTL pin to enable or disable regulation, regardless of the state of the OPERATION command. The CNTL pin can be configured as either active high or active low (inverted) logic.

7.4.3 Operation with OPERATION Control

According to the value in the ON_OFF_CONFIG register, the devices can be commanded to use the OPERATION command to enable or disable regulation, regardless of the state of the CNTL signal.

7.4.4 Operation with CNTL and OPERATION Control

According to the value in the ON_OFF_CONFIG register, the devices can be commanded to require both a signal on the CNTL pin, and the OPERATION command to enable or disable regulation.

7.5.1 Supported PMBus Commands

The commands listed in Table 5 are implemented as described to conform to the PMBus 1.3 specification. Table 5 also lists the default for the bit behavior and register values.

Table 6. Legend for Register Access Type

7.6.1 OPERATION (01h)

The OPERATION command turns the device output on or off in conjunction with input from the CNTL signal. It is also used to set the output voltage to the upper or lower margin voltages. The unit stays in the commanded operating mode until a subsequent OPERATION command or a change in the state of the CNTL pin instructs the device to change to another mode.

For PWM loop slave device, which is recognized during power-up calibration, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

7.6.2 ON_OFF_CONFIG (02h)

The ON_OFF_CONFIG command configures the combination of CNTL pin input and serial bus commands needed to turn the unit on and off. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL (11h) command. The default value in ON_OFF_CONFIG register is to have the device power up by CNTL pin only with the active high polarity and use the programmed turnoff delay (TOFF_DELAY) and ramp down (TOFF_FALL) for powering off the converter.

For PWM loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

7.6.3 CLEAR_FAULTS (03h)

The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status registers simultaneously. At the same time, the device negates (clears, releases) its SMBALERT signal output if the device is asserting the SMBALERT signal. The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. If the fault is still present when the bit is cleared, the fault bit is immediately reset and the host notified by the usual means.

7.6.4 WRITE_PROTECT (10h)

The WRITE_PROTECT command is used to control writing to the PMBus device. The intent of this command is to provide protection against accidental changes. This command is not intended to provide protection against deliberate or malicious changes to the device configuration or operation. All supported command parameters may have their parameters read, regardless of the WRITE_PROTECT settings. Write protection also prevents protected registers from being updated in the event of a RESTORE_DEFAULT_ALL. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

7.6.5 STORE_DEFAULT_ALL (11h)

The STORE_DEFAULT_ALL command stores all of the current storable register settings in the EEPROM memory as the new defaults on power up.

It is permissible to use this command while the device is switching. Note however that the device continues to switch but ignores all fault conditions until the internal store process has completed. Issuing STORE_DEFAULT_ALL also causes the device to be unresponsive through PMBus for a period of approximately 100 ms.

EEPROM programming faults cause the device to NACK and set the cml bit in the STATUS_BYTE and the mem bit in the STATUS_CML registers.

7.6.6 RESTORE_DEFAULT_ALL (12h)

The RESTORE_DEFAULT_ALL command restores all of the storable register settings from EEPROM memory to those registers which are unprotected according to current setting of WRITE_PROTECT. Issuing STORE_DEFAULT_ALL also causes the device to be unresponsive through PMBus for a period of approximately 100 ms.

7.6.7 STORE_USER_ALL (11h)

The STORE_USER_ALL command stores all of the current storable register settings in the EEPROM memory as the new defaults on power up.

It is permissible to use this command while the device is switching. Note however that the device continues to switch but ignores all fault conditions until the internal store process has completed. Issuing STORE_USER_ALL also causes the device to be unresponsive through PMBus for a period of approximately 100 ms.

EEPROM programming faults cause the device to NACK and set the cml bit in the STATUS_BYTE and the mem bit in the STATUS_CML registers.

This command shres the same harware implementation as STORE_DEFAULT_ALL.

7.6.8 RESTORE_USER_ALL (12h)

The RESTORE_USER_ALL command restores all of the storable register settings from EEPROM memory to those registers which are unprotected according to current setting of WRITE_PROTECT. Issuing STORE_USER_ALL also causes the device to be unresponsive through PMBus for a period of approximately 100 ms.

This command shres the same harware implementation as RESTORE_DEFAULT_ALL.

7.6.9 CAPABILITY (19h)

The CAPABILITY command provides a way for a host system to determine some key capabilities of this PMBus device.

The default values indicate that the device supports packet-error checking (PEC), a maximum bus speed of 400 kHz (SPD) and the SMBus alert-response protocol using SMBALERT.

7.6.10 SMBALERT_MASK (1Bh)

The SMBALERT_MASK command can be used to prevent a warning or fault condition from asserting the SMBALERT signal.

The bits in the mask byte align with the bits in the corresponding status register. For example, if the STATUS_TEMPERATURE command were sent with the mask byte 01000000b, then an Overtemperature Warning condition would be blocked from asserting SMBALERT. Please refer to the PMBus v1.3 specification - section 15.38 (SMBALERT_MASK Command) and the SMBus specification Block Write/Block Read protocol for further details.

There are 19 maskable SMBALERT sources in the TPS546C20A. Each of these 19 status conditions has an associated EEPROM backed mask bit. These sources are represnted and identified in the status register command descriptions by a particular status bit denoted as having EEPROM backup (for example a bit access of r/w^E). Writes and reads to SMBALERT_MASK command code accepts only the following as valid STATUS_x command codes:

• STATUS_WORD
• STATUS_VOUT
• STATUS_IOUT
• STATUS_INPUT
• STATUS_TEMPERATURE
• STATUS_CML
• STATUS_MFR_SPECIFIC

Attempting to write a mask byte for any STATUS_X command code other than this list causes the device to set the cml bit in the STATUS_BYTE and the ivd bit in the STATUS_CML registers, and triggers SMBALERT. Attempting to read a mask byte for any STATUS_x command code other than this list returns 00h for the mask byte. Refer to these individual command descriptions for further details on their specific SMBALERT masking capabilities.

There is 1 unique status bit in the TPS546C20A that warrants special clarification: PGOOD_Z (STATUS_WORD[10]) is maskable as an SMBALERT source through SMBALERT_MASK commands to STATUS_WORD. If the user wants to write, or read, the mask bit for PGOOD_Z, the user must put 79h in the STATUS_x COMMAND_CODE field of the SMBALERT_MASK command. PGOOD_Z SMBALERT_MASK bit default to 1.

7.6.11 VOUT_MODE (20h)

The PMBus specification dictates that the data word for the VOUT_MODE command is one byte that consists of a 3-bit mode and 5-bit exponent parameter, as shown below. The 3-bit mode sets whether the device uses the Linear or Direct modes for output voltage related commands. The 5-bit parameter sets the exponent value for the linear data mode. The mode and exponent parameters are fixed and do not permit the user to change the values.

For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

7.6.12 VOUT_COMMAND (21h)

The VOUT_COMMAND command sets the output voltage in volts. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command. The exponent is set be VOUT_MODE at –9 (equivalent of 1.953 mV/count). The programmed internal reference voltage is computed as:

For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

The range of valid VOUT_COMMAND values is dependent upon the configured VOUT_SCALE_LOOP (29h) as follows:

Any VOUT_COMMAND > 2816 (5.5-V maximum V_OUT equivalent) is treated as invalid data:

• NACK the data byte
• Do not update VOUT_COMMAND
• Set CML bit in STATUS_BYTE
• Set IVD bit in STATUS_CML

If the value programmed to VOUT_COMMAND exceeds the value stored in either VOUT_MIN or VOUT_MAX. In this case, VOUT_COMMAND will be set to the appropriate VOUT_MIN or VOUT_MAX value (which ever was violated). See the command descriptions for (28h) VOUT_MIN or (24h) VOUT_MAX for the specific status bits set in either case.

When using the VSEL function, at initial power-up. the Mantissa value decoded according to the appropriate VSEL resistor is written into the VOUT_COMMAND register as the initial default. This overwrites any value restored from EEPROM when the device AVIN is powered up.

7.6.13 VOUT_MAX (24h)

The VOUT_MAX command sets the maximum output voltage. The purpose is to protect the devices on the output rail supplied by this device from a higher than acceptable output voltage. VOUT_MAX imposes an upper bound to any attempt to program the output voltage to a VOUT_EQUIV setting by changing any of the following registers:

• VOUT_COMMAND
• VOUT_MAX
• VOUT_MIN
• OPERATION[5]
• OPERATION[4]
• VREF_TRIM
• STEP_VREF_MARGIN_HIGH
• STEP_VREF_MARGIN_LOW
• VOUT_SCALE_LOOP

The exponent is set be VOUT_MODE at –9 (equivalent of 1.953 mV/count). Use Equation 6 to calculate the programmed output voltage.

The range of valid VOUT_MAX values is dependent upon the configured (29h) VOUT_SCALE_LOOP as shown in Equation 7.

If, while the output voltage is turned on, any attempt is made to program: (1) VOUT_EQUIV to be greater than VOUT_MAX; (2) VOUT_MAX to be less than, or equal to, VOUT_MIN, or; (3) VOUT_MIN to be greater than, or equal to, VOUT_MAX – the device will:

• Clamp the internal reference voltage to VOUT_MAX × VOUT_SCALE_LOOP × VOUT_MODE value. In the event VOUT_MAX < VOUT_MIN, VOUT_MAX shall dominate.
• Sets the OTH (other) bit in the STATUS_BYTE
• Sets the VFW bit in the STATUS_WORD
• Sets the VOUT_MAX_MIN_Warning bit in the STATUS_VOUTregister
• Notifies the host through the SMBALERT pin

For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

7.6.14 VOUT_TRANSITION_RATE (27h)

The VOUT_TRANSITION_RATE command sets the rate of change in mV/µs of any output voltage change during normal operation (also includes vout changes in TOFF_DELAY state. In contrast the soft-start transition rate is controlled by TON_RISE and the TOFF_FALL transition rate is controlled by TOFF_FALL command).

For PWM loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

Only 8 fixed output voltage transition rates are available in the device. As such, the range of programmed V_OUT-transition rates are sub-divided into 8 buckets that then selects one of the 8 fixed V_OUT-transition rates. Programmed values are rounded to the nearest bucket/transition rate as outlined below:

7.6.15 VOUT_SCALE_LOOP (29h)

The VOUT_SCALE_LOOP command is equal to the feedback resistor ratio (R_BIAS / (R_BIAS + R1) in the configuration shown in Figure 25). This command is limited to only 3 possible options/ratios: 1 (default, no R_BIAS needed), 0.5, and 0.25. Attempting to write a value unequal to one of these three options cause the device to set the cml bit in the STATUS_BYTE, and the ivd bit in the STATUS_CML registers. Additionally, SMBALERT is asserted and the value of VOUT_SCALE_LOOP remains unchanged. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

For the range checking to work properly and to avoid invalid data scenarios:

• VOUT_SCALE_LOOP should be changed first, if needed.
• VOUT_MIN and VOUT_MAX should be changed after VOUT_SCALE_LOOP, if needed.
• Additionally, it is assumed that VOUT_SCALE_LOOP will be programmed before the output is turned on; but, the hardware will not do anything to prohibit changing VOUT_SCALE_LOOP in any state.

7.6.16 VOUT_MIN (2Bh)

The VOUT_MIN command sets the minimum output voltage. The purpose is to protect the devices on the output rail supplied by this device from a lower than acceptable output voltage. VOUT_MIN imposes a lower bound to any attempt to program the output voltage to a VOUT_EQUIV setting by changing any of the following registers:

• VOUT_COMMAND
• VOUT_MAX
• VOUT_MIN
• OPERATION[5]
• OPERATION[4]
• VREF_TRIM
• STEP_VREF_MARGIN_HIGH
• STEP_VREF_MARGIN_LOW
• VOUT_SCALE_LOOP

The exponent is set be VOUT_MODE at –9 (equivalent of 1.953 mV/count). Use Equation 8 to calculate the programmed output voltage.

The range of valid VOUT_MIN values is dependent upon the configured (29h) VOUT_SCALE_LOOP as shown in Equation 9.

If, while the output voltage is turned on, any attempt is made to program: (1) VOUT_EQUIV to be less than VOUT_MIN, the device will:

• Clamp the internal reference voltage to VOUT_MIN × VOUT_SCALE_LOOP × VOUT_MODE value. In the event VOUT_MAX < VOUT_MIN, VOUT_MAX shall dominate.
• Sets the OTH (other) bit in the STATUS_BYTE
• Sets the VFW bit in the STATUS_WORD
• Sets the VOUT_MAX_MIN_Warning bit in the STATUS_VOUTregister
• Notifies the host through the SMBALERT pin

For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

7.6.17 VIN_ON (35h)

The VIN_ON command sets the value of the input voltage at which the unit should start operation assuming all other required startup conditions are met. Values are mapped to the nearest supported increment. Values outside the supported range are treated as invalid data and cause the device set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers, and trigger SMBALERT signal. The value of VIN_ON remains unchanged on an out-of-range write attempt. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

The supported VIN_ON values are shown in Table 7:

VIN_ON must be set higher than VIN_OFF. Attempting to write either VIN_ON lower than VIN_OFF or VIN_OFF higher than VIN_ON results in the new value being rejected, SMBALERT signal being asserted along with the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

The data word that accompanies this command is divided into a fixed 5-bit exponent and an 11-bit mantissa. The four most significant bits of the mantissa are fixed, while the lower 4 bits may be altered.

7.6.18 VIN_OFF (36h)

The VIN_OFF command sets the value of the input voltage at which the unit should stop operation. Values are mapped to the nearest supported increment. Values outside the supported range is treated as invalid data and causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers, and trigger SMBALERT signal. The value of VIN_OFF remains unchanged during an out-of-range write attempt. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

The supported VIN_OFF values are shown in Table 8:

VIN_ON must be set higher than VIN_OFF. Attempting to write either VIN_ON lower than VIN_OFF or VIN_OFF higher than VIN_ON results in the new value being rejected, SMBALERT being asserted along with the cml bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

The data word that accompanies this command is divided into a fixed 5 bit exponent and an 11 bit mantissa. The 4 most significant bits of the mantissa are fixed, while the lower 7 bits may be altered.

7.6.19 IOUT_CAL_OFFSET (39h)

The IOUT_CAL_OFFSET command is used to compensate for offset errors in the READ_IOUT results and the IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT thresholds. The units are amperes. The default setting is 0 A. The resolution of the argument for this command is 62.5 mA and the range is +3.9375 A to –4 A. Values written outside of this range alias into the supported range. This occurs because the read-only bits are fixed. The exponent is always –4 and the 5 MSB bits of the Mantissa are always equal to the sign bit. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

7.6.20 VOUT_OV_FAULT_RESPONSE (41h)

The VOUT_OV_FAULT_RESPONSE command instructs the device on what action to take in response to an Output Over Voltage Fault based on MFR_SPECIFIC_07 (PCT_OV_UV_WRN_FLT_LIMITS). The device also:

• Sets the OVF bit in the STATUS_BYTE
• Sets the VFW bit in the STATUS_WORD
• Sets the OVF bit in the STATUS_VOUT register, and
• Notifies the host by asserting SMBALERT

For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

The default response to a output overvoltage fault is to shut down and restart with 7 × TON_RISE time delay.

These bits are direct reflections of the RS[2] (bit 5) value in this register.

7.6.21 VOUT_UV_FAULT_RESPONSE (45h)

The VOUT_UV_FAULT_RESPONSE command instructs the device on what action to take in response to an Output Under Voltage Fault based on MFR_SPECIFIC_07 (PCT_OV_UV_WRN_FLT_LIMITS). The device also:

• Sets the oth bit in the STATUS_BYTE
• Sets the VFW bit in the STATUS_WORD
• Sets the UVF bit in the STATUS_VOUT register, and
• Notifies the host by asserting SMBALERT

For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

The default response to a output undervoltage fault is to shut down and restart with 7 × TON_RISE time delay.

7.6.22 IOUT_OC_FAULT_LIMIT (46h)

The IOUT_OC_FAULT_LIMIT command sets the value of the output current, in amperes, that causes the overcurrent detector to indicate an overcurrent fault condition. The IOUT_OC_FAULT_LIMIT should be set equal to or greater than the IOUT_OC_WARN_LIMIT. Writing a value to IOUT_OC_FAULT_LIMIT less than IOUT_OC_WARN_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALERT signal. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command. Since 2-LSBs are not stored in EEPROM, on STORE, always round up. If IOUT_OC_FAULT_LIMIT [1:0] > 0, add 1 to IOUT_OC_FAULT_LIMIT [6:2]

The IOUT_OC_FAULT_LIMIT takes a two-byte data word formatted as shown below:

7.6.22.2 Mantissa

The upper four bits are fixed at 0.

The lower seven bits are programmable.

Use Equation 10 to calculate the actual output current for a given mantissa and exponent.

Equation 10.

The default values and allowable ranges for each device are summarized below:

DEVICE	OC_FAULT_LIMIT			UNIT
	MIN	DEFAULT	MAX
TPS546C20A	5	42	52	A

7.6.23 IOUT_OC_FAULT_RESPONSE (47h)

The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an IOUT_OC_FAULT_LIMIT. The device also:

• Sets the OCF bit in the STATUS_BYTE
• Sets the OCFW bit in the STATUS_WORD
• Sets the OCF bit in the STATUS_IOUT register, and
• Notifies the host by asserting SMBALERT

The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

The default response to an overcurrent fault is to shut down and restart with 7 × TON_RISE time delay.

7.6.24 IOUT_OC_WARN_LIMIT (4Ah)

The IOUT_OC_WARN_LIMIT command sets the value of the output current, in amperes, that causes the overcurrent detector to indicate an overcurrent warning. When this current level is exceeded the device:

• Sets the oth bit in the STATUS_BYTE
• Sets the OCFW bit in the STATUS_WORD
• Sets the OCW bit in the STATUS_IOUT register, and
• Notifies the host by asserting SMBALERT

The IOUT_OC_WARN_LIMIT threshold should always be set to less than or equal to the IOUT_OC_FAULT_LIMIT. Writing a value to IOUT_OC_WARN_LIMIT greater than IOUT_OC_FAULT_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALERT signal. In such case, the register content will remain unchanged. This behavior can be overridden by the user setting Data Limit Override (DLO) in MFR_SPECIFIC_21[4].

The default IOUT_OC_WARN_LIMIT is always set to relative to 87.5% of the OCF value. Because the IOUT_OC_WARN_LIMIT is not stored in EEPROM, the IOUT_OC_WARN_LIMIT register is set to 12.5% less than the stored OCF threshold upon any RESTORE from EEPROM (reset_restore, or RESTORE_DEFAULT_ALL command). The digital math to achieve this is: OCW_default = (OCF – OCF/8).

The IOUT_OC_WARN_LIMIT takes a two byte data word formatted as shown below:

7.6.24.2 Mantissa

The upper four bits are fixed at 0.

Lower seven bits are programmable.

The actual output warning current level for a given mantissa and exponent is:

Equation 11.

The default values and allowable ranges for each device are summarized below:

DEVICE	OC_WARN_LIMIT			UNIT
	MIN	DEFAULT	MAX
TPS546C20A	4	37	50	A

7.6.25 OT_FAULT_LIMIT (4Fh)

The OT_FAULT_LIMIT command sets the value of the temperature, in degrees Celsius, that causes an overtemperature fault condition, when the sensed temperature from the external sensor exceeds this limit.

The OT_FAULT_LIMIT must always be greater than the OT_WARN_LIMIT. Writing a value to OT_FAULT_LIMIT less than or equal to OT_WARN_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as asserts the SMBALERT signal. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

The OT_FAULT_LIMIT takes a two byte data word formatted as shown below.

7.6.26 OT_FAULT_RESPONSE (50h)

The OT_FAULT_RESPONSE command instructs the device on what action to take in response to an OT_FAULT_LIMIT. The device also:

• Sets the OTFW bit in the STATUS_BYTE
• Sets the OTF bit in the STATUS_TEMPERATURE
• Notifies the host by asserting SMBALERT

When the overtemperature fault is tripped, the fault flag is latched until the external sensed temperature decreases 20°C from the OT_FAULT_LIMIT.

The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

The default response to an over temperature fault is to ignore. Fixed Bandgap Detected Overtemperature faults are never ignored. The Bandgap OT faults always respond in a shutdown and attempted restart once the part cools.

7.6.27 OT_WARN_LIMIT (51h)

The OT_WARN_LIMIT command sets the value of the temperature, in degrees Celsius, that causes an overtemperature warning condition, when the sensed temperature from the external sensor exceeds this limit. Upon triggering the overtemperature warning, the device takes the following actions:

• Sets the TEMPERATURE bit in the STATUS_BYTE
• Sets the OT Warning bit in the STATUS_TEMPERATURE
• Notifies the host by asserting SMBALERT

Once the overtemperature warning is tripped, the warning flag is latched until the external sensed temperature decreases 20°C from the OT_WARN_LIMIT.

The OT_WARN_LIMIT must always be less than the OT_FAULT_LIMIT. Writing a value to OT_WARN_LIMIT greater than or equal to OT_FAULT_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALERT signal. In such case, the register content will remain unchanged. This behavior can be overridden by the user setting Data Limit Override (DLO) in MFR_SPECIFIC_21[4].

The default OT_WARN_LIMIT is mathematically derived from the EEPROM backed OTF limit by subtracting 25 from (4Fh) OT_FAULT_LIMIT to reach the default OT_WARN_LIMIT. If the calculated OTW is less than 100°C, then the default value is set to 100°C. OTW=max(OTF-25, 100)

The OT_WARN_LIMIT takes a two byte data word formatted as shown below:

7.6.28 TON_DELAY (60h)

The TON_DELAY command sets the time in milliseconds, from when a start condition is received to when the output voltage starts to rise. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

The TON_DELAY command is formatted as a linear mode two’s complement binary integer.

Only 16 fixed TON_DELAY times are available in the device. As such, the range of programmed TON_DELAY settings are sub-divided into 16 buckets that then selects one of the 16 supported times. Programmed values are rounded to the nearest bucket/transition rate as outlined in the table Supported TON_DELAY Values:

7.6.29 TON_RISE (61h)

The TON_RISE command sets the time in milliseconds, from when the reference starts to rise until the voltage has entered the regulation band. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

Programming a value of 0 instructs the unit to bring its output voltage to the programmed regulation value as quickly as possible. For the TPS546C20A device, this results in an effective TON_RISE time of 1ms (fastest time supported).

If the soft-start detection feature is being used (SS pin not pulling up high), then the Mantissa value decoded or derived by from the appropriate SS resistor writes into the TON_RISE register as the initial default. Note: This write overwrites any value restored from the EEPROM restore operation at initial power-up.

The TON_RISE command is formatted as a linear mode two’s complement binary integer.

The supported TON_RISE times over PMBus are shown in Table 10:

7.6.30 TON_MAX_FAULT_LIMIT (62h)

The TON_MAX_FAULT_LIMIT command sets an UPPER limt in milliseconds, on how long the unit can attempt to power up the output without reaching the output undervoltage fault limit. The time begins counting as soon as the device enters the soft-start state begins to ramp the output. In other words, the TON_MAX_FAULT_LIMIT timer starts at the beginning of the TON_RISE state.

For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

When TON_MAX_FAULT_LIMIT is set to 0, the TON_MAX_FAULT timer is disabled, which means that there is no limit and that the unit can attempt to bring up the output voltage indefinitely.

The device does not prohibit setting TON_MAX_FAULT_LIMIT < TON_RISE, however, in this configuration, the device will trigger a TON_MAX_FAULT if the VOUT has not risen above the UVF threshold by 4 seconds after the TON_DELAY and TON_RISE times expire.

The TON_MAX_FAULT_LIMIT command is formatted as a linear mode two’s complement binary integer.

The supported TON_MAX_FAULT_LIMIT times over PMBus are shown in Supported TON_MAX_FAULT_LIMIT Values:

7.6.31 TON_MAX_FAULT_RESPONSE (63h)

The TON_MAX_FAULT_RESPONSE command instructs the device on what action to take in response to an TON_MAX_FAULT_LIMIT.

The device also:

• Sets the oth bit in the STATUS_BYTE
• Sets the VFW bit in the STATUS_WORD
• Sets the TONMAXF bit in the STATUS_VOUT register, and
• Notifies the host by asserting SMBALERT

For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

The default response to a TON_MAX_FAULT is to shut down and restart with 7 × TON_RISE time delay.

7.6.32 TOFF_DELAY (64h)

The TOFF_DELAY command sets the time in milliseconds, from when a stop condition is received and when the output voltage starts to fall. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

The TOFF_DELAY command is formatted as a linear mode two’s complement binary integer.

Only 16 fixed TOFF_DELAY times are available in the device. As such, the range of programmed TOFF_DELAY settings are sub-divided into 16 buckets that then selects one of the 16 supported times. Programmed values are rounded to the nearest bucket/transition rate as outlined in the table Supported TOFF_DELAY Values:

7.6.33 TOFF_FALL (65h)

The TOFF_FALL command sets the time in milliseconds, from the end of the TOFF_DELAY time until the voltage reaches 0 V. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

Programming a value of 0 instructs the unit to bring its output voltage down to 0 as quickly as possible. For the TPS546C20A device, this results in actively ramping down the output voltage in 1 ms (the fastest supported ramp down).

For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

The TOFF_FALL command is formatted as a linear mode two’s complement binary integer.

The supported TOFF_FALL times over PMBus are shown in Supported TOFF_FALL Values:

7.6.34 STATUS_BYTE (78h)

The STATUS_BYTE command returns one byte of information with a summary of the most critical device faults.

A 1 in any of these bit positions indicates that:

7.6.35 STATUS_WORD (79h)

The STATUS_WORD command returns two bytes of information with a summary of the device fault and warning conditions. The low byte is identical to the STATUS_BYTE above. The additional byte reports the warning conditions for output overvoltage and overcurrent, as well as the power good status of the converter.

A 1 in any of the high byte bit positions indicates that:

7.6.36 STATUS_VOUT (7Ah)

The STATUS_VOUT command returns one byte of information relating to the status of the output voltage related faults.

A 1 in any of these bit positions indicates that:

7.6.37 STATUS_IOUT (7Bh)

The STATUS_IOUT command returns one byte of information relating to the status of the output current related faults.

A 1 in any of these bit positions indicates that:

7.6.38 STATUS_INPUT (7Ch)

The STATUS_INPUT command returns one byte of information relating to the status of the input-related faults of the converter.

A 1 in any of these bit positions indicates that:

7.6.39 STATUS_TEMPERATURE (7Dh)

The STATUS_TEMPERATURE command returns one byte of information relating to the status of the external temperature related faults.

A 1 in any of these bit positions indicates that:

7.6.40 STATUS_CML (7Eh)

The STATUS_CML command returns one byte of information relating to the status of the communication-related faults of the converter.

A 1 in any of these bit positions indicates that:

7.6.41 STATUS_MFR_SPECIFIC (80h)

The STATUS_MFR_SPECIFIC command returns one byte of information relating to the status of manufacturer-specific faults or warnings.

A 1 in any of these bit positions indicates that:

7.6.42 READ_VOUT (8Bh)

The READ_VOUT commands returns two bytes of data in the linear data format that represent the output voltage of the converter. The output voltage is sensed at the remote sense amplifier output pin so voltage drop to the load is not accounted for. The data format is as shown below:

7.6.42.2 Mantissa

Use Equation 12 to calculate the output voltage.

Equation 12.

7.6.43 READ_IOUT (8Ch)

The READ_IOUT commands returns two bytes of data in the linear data format that represent the output current of the converter. The average output current is sensed according to the method described in Low-Side MOSFET Current Sensing and Overcurrent Protection. The data format is as shown below:

The device scales the output current before it reaches the internal analog to digital converter so that resolution of the output current read is 62.5 mA. The maximum value that can be reported is 40 A. The user must set the IOUT_CAL_OFFSET parameter correctly to obtain accurate results. Use Equation 13 to calculate the output current.

Equation 13.

7.6.44 READ_TEMPERATURE_1 (8Dh)

The READ_TEMPERATURE_1 command returns the external temperature in degrees Celsius.

7.6.45 PMBUS_REVISION (98h)

The PMBUS_REVISION command returns a single, unsigned binary byte that indicates that these devices are compatible with the 1.3 revision of the PMBus specification (Part I and Part II).

7.6.46 IC_DEVICE_ID (ADh)

Th IC_DEVICE_ID command is a read-only block-read command that returns a single word (16 bits) with the unique device-code identifier for each device for which this device can be configured. The BYTE_COUNT field in the block read command is 2 (indicating 2 bytes follow): low byte first, high byte second.

The default for the device identifier code is 4620h – Code Identifier for TPS546C20A.

7.6.47 IC_DEVICE_REV (AEh)

The IC_DEVICE_REV command is a read-only block-read command that returns a single word (16 bits) with the unique Device revision identifier. The DEVICE_REV starts at 0 with the first silicon and is incremented with each subsequent silicon revision. The BYTE_COUNT field in the Block Read command is 2 (indicating 2 bytes follow): low byte first, high byte second.

The default of the device identifier code is 0001b.

7.6.48 MFR_SPECIFIC_00 (D0h)

The MFR_SPECIFIC_00 command is dedicated as a user scratch pad. Only the lower 8 bits are writeable for users. This is a read word command, with only the lower 8 bits accessible. This command is not a read byte command. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

7.6.49 VREF_TRIM (MFR_SPECIFIC_04) (D4h)

The VREF_TRIM command applies a fixed offset voltage to the Error Amplifier reference (EA_REF) voltage. It is most typically used to trim the output voltage at the time the PMBus device is assembled into the end user’s system. The contents of this register can be stored to nonvolatile memory using the STORE_DEFAULT_ALL command.

For loop slave device, this command cannot be accessed. Any writes to this command will be ignored. An attempt to read or write this command will result in a NACK’d command, the reporting of an IVC fault, and triggering of SMB_ALERT.

The settings of the VOUT_MODE command determine the effect of VREF_TRIM command. In this device, the VOUT_MODE is fixed to Linear with an exponent of –9 (decimal).

The maximum trim ranges between –64*1.953 mV to +63*1.953 mV in 1.953-mV steps.

If a value outside this range is given with this command, the device sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML.

The value of EA_REF including VREF_TRIM is also limited by the values of VOUT_MAX, VOUT_MIN, VOUT_COMMAND, VOUT_SCALE_LOOP and STEP_VREF_MARGIN_HIGH/LOW. See VOUT_MAX and VOUT_MIN for additional details.

The EA_REF voltage transition occurs at the rate determined by the current state:

• Soft-Start: TON_RISE command
• Steady-State: VOUT_TRANSITION_RATE command
• TOFF_DELAY: VOUT_TRANSITION_RATE command
• Soft-Stop: TOFF_FALL command

The VREF_TRIM has two data bytes formatted as two’s complement binary integer and can have positive and negative values.