SLVSH95 July 2024 TPS546C25
ADVANCE INFORMATION
| CMD Address: | 7Ch |
| Write Transaction: | Write Byte |
| Read Transaction: | Read Byte |
| Format: | Unsigned Binary (1 byte) |
| NVM Back-up: | Yes |
| Updates: | On-the-fly |
The STATUS_INPUT command returns one data byte with contents as follows. The status bits remain latched after the fault condition is no longer present (as conveyed by digital input fault/warning signal). All supported bits may be cleared either by CLEAR_FAULTS, turning on the output through the mechanism programmed into ON_OFF_CONFIG, or individually by writing 1b to the STATUS_INPUT register in their position, per the PMBus 1.3.1 Part II specification section 10.2.3.
None of these bits is affected by the state of SMBALERT_MASK. However, if the corresponding fault/warning disable bits in the FAULT_CTRL register is set, then the corresponding status bits will also be blocked in addition to blocking the response from that fault.
Return to Supported PMBus Commands.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RW1C | R | R | R | RW1C | R | R | R |
| PVIN_OVF | 0 | 0 | 0 | LOW_VIN | 0 | 0 | 0 |
| LEGEND: R/W1C = Read/Write 1 to clear; R = Read only |
Bit | Field | Access | Reset | Description |
|---|---|---|---|---|
| 7 | PVIN_OVF | R/W1C | 0b | 0b: Latched flag indicating an input overvoltage
fault has NOT occured. 1b: Latched flag indicating an input overvoltage fault has occured. |
| 6:4 | Not Supported | R | 000b | Not supported and always set to 0. |
| 3 | LOW_VIN | R/W1C | 0b | This bit indicates the status of the PVIN voltage relative to VIN_ON and VIN_OFF. During the initial power up, LOW_VIN is not latched and does not assert SMB_ALERT#. Once PVIN exceeds VIN_ON for the first time, any subsequent PVIN < VIN_OFF events will be latched and assert SMB_ALERT#. 0b: PVIN is greater than
VIN_ON. |
| 2:0 | Not Supported | R | 000b | Not supported and always set to 0. |